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1 1 : /*
2 : * Copyright (c) 2023 Nuvoton Technology Corporation.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : /**
8 : * @file
9 : * @brief Header file for NPCX flash extended operations.
10 : * @ingroup npcx_flash_ex_op
11 : */
12 :
13 : #ifndef __ZEPHYR_INCLUDE_DRIVERS_NPCX_FLASH_API_EX_H__
14 : #define __ZEPHYR_INCLUDE_DRIVERS_NPCX_FLASH_API_EX_H__
15 :
16 : /**
17 : * @brief Extended operations for NPCX flash controllers.
18 : * @defgroup npcx_flash_ex_op NPCX
19 : * @ingroup flash_ex_op
20 : * @{
21 : */
22 :
23 : #ifdef __cplusplus
24 : extern "C" {
25 : #endif
26 :
27 : #include <zephyr/drivers/flash.h>
28 :
29 : /**
30 : * @brief Enumeration for NPCX flash extended operations.
31 : */
32 1 : enum flash_npcx_ex_ops {
33 : /**
34 : * User Mode Access (UMA) mode execution.
35 : *
36 : * Execute a SPI transaction via User Mode Access (UMA) mode. Users can
37 : * perform a customized SPI transaction to read or write the device's
38 : * configuration such as status registers of nor flash, power on/off,
39 : * and so on.
40 : *
41 : * @param in Pointer to a @ref npcx_ex_ops_uma_in structure specifying the
42 : * UMA transaction.
43 : * @param out Pointer to a @ref npcx_ex_ops_uma_out structure to store the
44 : * result of the UMA transaction.
45 : */
46 : FLASH_NPCX_EX_OP_EXEC_UMA = FLASH_EX_OP_VENDOR_BASE,
47 : /**
48 : * Configure specific operation for Quad-SPI nor flash.
49 : *
50 : * It configures specific operation for Quad-SPI nor flash such as lock
51 : * or unlock UMA mode, set write protection pin of internal flash, and
52 : * so on.
53 : *
54 : * @param in Pointer to a @ref npcx_ex_ops_qspi_oper_in structure specifying the
55 : * operation to set.
56 : */
57 : FLASH_NPCX_EX_OP_SET_QSPI_OPER,
58 : /**
59 : * Get specific operation for Quad-SPI nor flash.
60 : *
61 : * It returns current specific operation for Quad-SPI nor flash.
62 : *
63 : * @param out Pointer to a @ref npcx_ex_ops_qspi_oper_out structure to store the
64 : * result of the operation.
65 : */
66 : FLASH_NPCX_EX_OP_GET_QSPI_OPER,
67 : };
68 :
69 : /**
70 : * @brief Input parameters for @ref FLASH_NPCX_EX_OP_EXEC_UMA operation.
71 : *
72 : * Defines the content of a UMA transaction.
73 : */
74 1 : struct npcx_ex_ops_uma_in {
75 1 : uint8_t opcode; /**< SPI opcode (command byte). */
76 1 : uint8_t *tx_buf; /**< Pointer to transmit buffer (may be NULL). */
77 1 : size_t tx_count; /**< Number of bytes to transmit. */
78 1 : uint32_t addr; /**< Address for address phase. */
79 1 : size_t addr_count; /**< Number of address bytes (0–4). */
80 1 : size_t rx_count; /**< Number of bytes expected to be read. */
81 : };
82 :
83 : /**
84 : * @brief Output parameters for @ref FLASH_NPCX_EX_OP_EXEC_UMA operation.
85 : *
86 : * Defines where received data is stored.
87 : */
88 1 : struct npcx_ex_ops_uma_out {
89 1 : uint8_t *rx_buf; /**< Pointer to receive buffer (must be large enough). */
90 : };
91 :
92 : /**
93 : * @brief Input parameters for @ref FLASH_NPCX_EX_OP_SET_QSPI_OPER operation.
94 : *
95 : * Used to enable or disable specific NPCX Quad-SPI operations.
96 : */
97 1 : struct npcx_ex_ops_qspi_oper_in {
98 1 : bool enable; /**< True to enable, false to disable. */
99 1 : uint32_t mask; /**< Mask of operations to configure. */
100 : };
101 :
102 : /**
103 : * @brief Output parameters for @ref FLASH_NPCX_EX_OP_GET_QSPI_OPER operation.
104 : *
105 : * Used to report the current QSPI operation state.
106 : */
107 1 : struct npcx_ex_ops_qspi_oper_out {
108 1 : uint32_t oper; /**< Bitfield of currently active operations. */
109 : };
110 :
111 : /**
112 : * @name NPCX QSPI operation control bits
113 : * @{
114 : */
115 1 : #define NPCX_EX_OP_LOCK_UMA BIT(0) /**< Lock/Unlock UMA mode */
116 1 : #define NPCX_EX_OP_INT_FLASH_WP BIT(1) /**< Issue write protection of internal flash */
117 : /** @} */
118 :
119 : #ifdef __cplusplus
120 : }
121 : #endif
122 :
123 : /**
124 : * @}
125 : */
126 :
127 : #endif /* __ZEPHYR_INCLUDE_DRIVERS_NPCX_FLASH_API_EX_H__ */
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