Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2016 Linaro Limited.
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : #ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_CMSDK_AHB_H_
       7             : #define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_CMSDK_AHB_H_
       8             : 
       9             : #include <zephyr/drivers/gpio.h>
      10             : 
      11             : #ifdef __cplusplus
      12             : extern "C" {
      13             : #endif
      14             : 
      15             : /* ARM LTD CMSDK AHB General Purpose Input/Output (GPIO) */
      16           0 : struct gpio_cmsdk_ahb {
      17             :         /* Offset: 0x000 (r/w) data register */
      18           0 :         volatile uint32_t data;
      19             :         /* Offset: 0x004 (r/w) data output latch register */
      20           0 :         volatile uint32_t dataout;
      21           0 :         volatile uint32_t reserved0[2];
      22             :         /* Offset: 0x010 (r/w) output enable set register */
      23           0 :         volatile uint32_t outenableset;
      24             :         /* Offset: 0x014 (r/w) output enable clear register */
      25           0 :         volatile uint32_t outenableclr;
      26             :         /* Offset: 0x018 (r/w) alternate function set register */
      27           0 :         volatile uint32_t altfuncset;
      28             :         /* Offset: 0x01c (r/w) alternate function clear register */
      29           0 :         volatile uint32_t altfuncclr;
      30             :         /* Offset: 0x020 (r/w) interrupt enable set register */
      31           0 :         volatile uint32_t intenset;
      32             :         /* Offset: 0x024 (r/w) interrupt enable clear register */
      33           0 :         volatile uint32_t intenclr;
      34             :         /* Offset: 0x028 (r/w) interrupt type set register */
      35           0 :         volatile uint32_t inttypeset;
      36             :         /* Offset: 0x02c (r/w) interrupt type clear register */
      37           0 :         volatile uint32_t inttypeclr;
      38             :         /* Offset: 0x030 (r/w) interrupt polarity set register */
      39           0 :         volatile uint32_t intpolset;
      40             :         /* Offset: 0x034 (r/w) interrupt polarity clear register */
      41           0 :         volatile uint32_t intpolclr;
      42             :         union {
      43             :                 /* Offset: 0x038 (r/ ) interrupt status register */
      44           0 :                 volatile uint32_t intstatus;
      45             :                 /* Offset: 0x038 ( /w) interrupt clear register */
      46           0 :                 volatile uint32_t  intclear;
      47           0 :         };
      48           0 :         volatile uint32_t reserved1[241];
      49             :         /* Offset: 0x400 - 0x7fc lower byte masked access register (r/w) */
      50           0 :         volatile uint32_t lb_masked[256];
      51             :         /* Offset: 0x800 - 0xbfc upper byte masked access register (r/w) */
      52           0 :         volatile uint32_t ub_masked[256];
      53             : };
      54             : 
      55             : #ifdef __cplusplus
      56             : }
      57             : #endif
      58             : 
      59             : #endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_CMSDK_AHB_H_ */