Line data Source code
1 0 : /*
2 : * Copyright 2024 Meta Platforms
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DRIVERS_I3C_HDR_DDR_H_
8 : #define ZEPHYR_INCLUDE_DRIVERS_I3C_HDR_DDR_H_
9 :
10 : /**
11 : * @brief I3C HDR DDR API
12 : * @defgroup i3c_hdr_ddr I3C HDR DDR API
13 : * @ingroup i3c_interface
14 : * @{
15 : */
16 :
17 : #include <errno.h>
18 : #include <stddef.h>
19 : #include <stdint.h>
20 :
21 : #include <zephyr/drivers/i3c.h>
22 :
23 : #ifdef __cplusplus
24 : extern "C" {
25 : #endif
26 :
27 : /**
28 : * @brief Write a set amount of data to an I3C target device with HDR DDR.
29 : *
30 : * This routine writes a set amount of data synchronously.
31 : *
32 : * @param target I3C target device descriptor.
33 : * @param cmd 7-bit command code
34 : * @param buf Memory pool from which the data is transferred.
35 : * @param num_bytes Number of bytes to write.
36 : *
37 : * @retval 0 If successful.
38 : * @retval -EBUSY Bus is busy.
39 : * @retval -EIO General input / output error.
40 : */
41 1 : static inline int i3c_hdr_ddr_write(struct i3c_device_desc *target, uint8_t cmd, uint8_t *buf,
42 : uint32_t num_bytes)
43 : {
44 : struct i3c_msg msg;
45 :
46 : msg.buf = buf;
47 : msg.len = num_bytes;
48 : msg.flags = I3C_MSG_WRITE | I3C_MSG_STOP | I3C_MSG_HDR;
49 : msg.hdr_mode = I3C_MSG_HDR_DDR;
50 : msg.hdr_cmd_code = cmd;
51 :
52 : return i3c_transfer(target, &msg, 1);
53 : }
54 :
55 : /**
56 : * @brief Read a set amount of data from an I3C target device with HDR DDR.
57 : *
58 : * This routine reads a set amount of data synchronously.
59 : *
60 : * @param target I3C target device descriptor.
61 : * @param cmd 7-bit command code
62 : * @param buf Memory pool that stores the retrieved data.
63 : * @param num_bytes Number of bytes to read.
64 : *
65 : * @retval 0 If successful.
66 : * @retval -EBUSY Bus is busy.
67 : * @retval -EIO General input / output error.
68 : */
69 1 : static inline int i3c_hdr_ddr_read(struct i3c_device_desc *target, uint8_t cmd, uint8_t *buf,
70 : uint32_t num_bytes)
71 : {
72 : struct i3c_msg msg;
73 :
74 : msg.buf = buf;
75 : msg.len = num_bytes;
76 : msg.flags = I3C_MSG_READ | I3C_MSG_STOP | I3C_MSG_HDR;
77 : msg.hdr_mode = I3C_MSG_HDR_DDR;
78 : msg.hdr_cmd_code = cmd;
79 :
80 : return i3c_transfer(target, &msg, 1);
81 : }
82 :
83 : /**
84 : * @brief Write then read data from an I3C target device with HDR DDR.
85 : *
86 : * This supports the common operation "this is what I want", "now give
87 : * it to me" transaction pair through a combined write-then-read bus
88 : * transaction.
89 : *
90 : * @param target I3C target device descriptor.
91 : * @param write_buf Pointer to the data to be written
92 : * @param num_write Number of bytes to write
93 : * @param read_cmd 7-bit command code for read
94 : * @param read_buf Pointer to storage for read data
95 : * @param num_read Number of bytes to read
96 : * @param write_cmd 7-bit command code for write
97 : *
98 : * @retval 0 if successful
99 : * @retval -EBUSY Bus is busy.
100 : * @retval -EIO General input / output error.
101 : */
102 1 : static inline int i3c_hdr_ddr_write_read(struct i3c_device_desc *target, const void *write_buf,
103 : size_t num_write, uint8_t read_cmd, void *read_buf,
104 : size_t num_read, uint8_t write_cmd)
105 : {
106 : struct i3c_msg msg[2];
107 :
108 : msg[0].buf = (uint8_t *)write_buf;
109 : msg[0].len = num_write;
110 : msg[0].flags = I3C_MSG_WRITE | I3C_MSG_HDR;
111 : msg[0].hdr_mode = I3C_MSG_HDR_DDR;
112 : msg[0].hdr_cmd_code = write_cmd;
113 :
114 : msg[1].buf = (uint8_t *)read_buf;
115 : msg[1].len = num_read;
116 : msg[1].flags = I3C_MSG_RESTART | I3C_MSG_READ | I3C_MSG_HDR | I3C_MSG_STOP;
117 : msg[1].hdr_mode = I3C_MSG_HDR_DDR;
118 : msg[1].hdr_cmd_code = read_cmd;
119 :
120 : return i3c_transfer(target, msg, 2);
121 : }
122 :
123 : #ifdef __cplusplus
124 : }
125 : #endif
126 :
127 : /**
128 : * @}
129 : */
130 :
131 : #endif /* ZEPHYR_INCLUDE_DRIVERS_I3C_HDR_DDR_H_ */
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