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1 0 : /* 2 : * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. 3 : * 4 : * SPDX-License-Identifier: Apache-2.0 5 : */ 6 : 7 : #ifndef ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ 8 : #define ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ 9 : 10 : #include <stdint.h> 11 : #include <stdbool.h> 12 : #include <soc.h> 13 : /* 14 : * Interrupt allocation flags - These flags can be used to specify 15 : * which interrupt qualities the code calling esp_intr_alloc* needs. 16 : */ 17 : 18 : /* Keep the LEVELx values as they are here; they match up with (1<<level) */ 19 0 : #define ESP_INTR_FLAG_LEVEL1 (1<<1) /* Accept a Level 1 int vector, lowest priority */ 20 0 : #define ESP_INTR_FLAG_LEVEL2 (1<<2) /* Accept a Level 2 int vector */ 21 0 : #define ESP_INTR_FLAG_LEVEL3 (1<<3) /* Accept a Level 3 int vector */ 22 0 : #define ESP_INTR_FLAG_LEVEL4 (1<<4) /* Accept a Level 4 int vector */ 23 0 : #define ESP_INTR_FLAG_LEVEL5 (1<<5) /* Accept a Level 5 int vector */ 24 0 : #define ESP_INTR_FLAG_LEVEL6 (1<<6) /* Accept a Level 6 int vector */ 25 0 : #define ESP_INTR_FLAG_NMI (1<<7) /* Accept a Level 7 int vector, highest priority */ 26 0 : #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ 27 0 : #define ESP_INTR_FLAG_EDGE (1<<9) /* Edge-triggered interrupt */ 28 0 : #define ESP_INTR_FLAG_IRAM (1<<10) /* ISR can be called if cache is disabled */ 29 0 : #define ESP_INTR_FLAG_INTRDISABLED (1<<11) /* Return with this interrupt disabled */ 30 : 31 : /* Low and medium prio interrupts. These can be handled in C. */ 32 0 : #define ESP_INTR_FLAG_LOWMED (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) 33 : 34 : /* High level interrupts. Need to be handled in assembly. */ 35 0 : #define ESP_INTR_FLAG_HIGH (ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \ 36 : ESP_INTR_FLAG_NMI) 37 : 38 : /* Mask for all level flags */ 39 0 : #define ESP_INTR_FLAG_LEVELMASK (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \ 40 : ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \ 41 : ESP_INTR_FLAG_NMI) 42 : 43 : /* 44 : * Get the interrupt flags from the supplied priority. 45 : */ 46 0 : #define ESP_PRIO_TO_FLAGS(priority) \ 47 : ((priority) > 0 ? ((1 << (priority)) & ESP_INTR_FLAG_LEVELMASK) : 0) 48 : 49 : /* 50 : * Check interrupt flags from input and filter unallowed values. 51 : */ 52 0 : #define ESP_INT_FLAGS_CHECK(int_flags) ((int_flags) & ESP_INTR_FLAG_SHARED) 53 : 54 : 55 : /* Function prototype for interrupt handler function */ 56 0 : typedef void (*isr_handler_t)(const void *arg); 57 : 58 : /** 59 : * @brief Initializes interrupt table to its defaults 60 : */ 61 1 : void esp_intr_initialize(void); 62 : 63 : /** 64 : * @brief Allocate an interrupt with the given parameters. 65 : * 66 : * This finds an interrupt that matches the restrictions as given in the flags 67 : * parameter, maps the given interrupt source to it and hooks up the given 68 : * interrupt handler (with optional argument) as well. If needed, it can return 69 : * a handle for the interrupt as well. 70 : * 71 : * @param source The interrupt source. 72 : * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the 73 : * choice of interrupts that this routine can choose from. If this value 74 : * is 0, it will default to allocating a non-shared interrupt of level 75 : * 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared 76 : * interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return 77 : * from this function with the interrupt disabled. 78 : * @param handler The interrupt handler. 79 : * @param arg Optional argument for passed to the interrupt handler 80 : * @param ret_handle Pointer to a struct intr_handle_data_t pointer to store a handle that can 81 : * later be used to request details or free the interrupt. Can be NULL if no handle 82 : * is required. 83 : * 84 : * @return -EINVAL if the combination of arguments is invalid. 85 : * -ENODEV No free interrupt found with the specified flags 86 : * 0 otherwise 87 : */ 88 1 : int esp_intr_alloc(int source, 89 : int flags, 90 : isr_handler_t handler, 91 : void *arg, 92 : void **ret_handle); 93 : 94 : /** 95 : * @brief Disable the interrupt associated with the source 96 : * 97 : * @param source The interrupt source 98 : * 99 : * @return -EINVAL if the combination of arguments is invalid. 100 : * 0 otherwise 101 : */ 102 1 : int esp_intr_disable(int source); 103 : 104 : /** 105 : * @brief Enable the interrupt associated with the source 106 : * 107 : * @param source The interrupt source 108 : * @return -EINVAL if the combination of arguments is invalid. 109 : * 0 otherwise 110 : */ 111 1 : int esp_intr_enable(int source); 112 : 113 : /** 114 : * @brief Gets the current enabled interrupts 115 : * 116 : * @param status_mask_number the status mask can be 0 or 1 117 : * @return bitmask of enabled interrupt sources 118 : */ 119 1 : uint32_t esp_intr_get_enabled_intmask(int status_mask_number); 120 : 121 : #endif /* ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ */