Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2025 Renesas Electronics Corporation
       3              :  * SPDX-License-Identifier: Apache-2.0
       4              :  */
       5              : 
       6              : #ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RX_ICU_H_
       7              : #define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RX_ICU_H_
       8              : 
       9            0 : #define IRQ_CFG_PCLK_DIV1  (0)
      10            0 : #define IRQ_CFG_PCLK_DIV8  (1)
      11            0 : #define IRQ_CFG_PCLK_DIV32 (2)
      12            0 : #define IRQ_CFG_PCLK_DIV64 (3)
      13              : 
      14            0 : enum icu_irq_mode {
      15              :         ICU_LOW_LEVEL,
      16              :         ICU_FALLING,
      17              :         ICU_RISING,
      18              :         ICU_BOTH_EDGE,
      19              :         ICU_MODE_NONE,
      20              : };
      21              : 
      22            0 : enum icu_dig_filt {
      23              :         DISENABLE_DIG_FILT,
      24              :         ENABLE_DIG_FILT,
      25              : };
      26              : 
      27            0 : typedef struct rx_irq_dig_filt_s {
      28            0 :         uint8_t filt_clk_div; /* PCLK divisor setting for the input pin digital filter. */
      29            0 :         uint8_t filt_enable;  /* Filter enable setting for the input pin digital filter. */
      30            0 : } rx_irq_dig_filt_t;
      31              : 
      32            0 : extern void rx_icu_clear_ir_flag(unsigned int irqn);
      33            0 : extern int rx_icu_get_ir_flag(unsigned int irqn);
      34            0 : extern int rx_icu_set_irq_control(unsigned int pin_irqn, enum icu_irq_mode mode);
      35            0 : extern void rx_icu_set_irq_dig_filt(unsigned int pin_irqn, rx_irq_dig_filt_t dig_filt);
      36              : 
      37              : #endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RX_ICU_H_ */