Line data    Source code

       1           0 : /* Copyright (C) 2023 BeagleBoard.org Foundation
       2             :  * Copyright (C) 2023 S Prashanth
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef ZEPHYR_DRIVERS_INTC_VIM_H_
       8             : #define ZEPHYR_DRIVERS_INTC_VIM_H_
       9             : 
      10             : #include <stdint.h>
      11             : 
      12             : #include <zephyr/devicetree.h>
      13             : #include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
      14             : #include <zephyr/sys/util_macro.h>
      15             : 
      16           0 : #define VIM_BASE_ADDR             DT_REG_ADDR(DT_INST(0, ti_vim))
      17             : 
      18           0 : #define VIM_MAX_IRQ_PER_GROUP     (32)
      19           0 : #define VIM_MAX_GROUP_NUM         ((uint32_t)(CONFIG_NUM_IRQS / VIM_MAX_IRQ_PER_GROUP))
      20             : 
      21           0 : #define VIM_GET_IRQ_GROUP_NUM(n)  ((uint32_t)((n) / VIM_MAX_IRQ_PER_GROUP))
      22           0 : #define VIM_GET_IRQ_BIT_NUM(n)    ((uint32_t)((n) % VIM_MAX_IRQ_PER_GROUP))
      23             : 
      24           0 : #define VIM_PRI_INT_MAX           (15)
      25             : 
      26           0 : #define VIM_PID             (VIM_BASE_ADDR + 0x0000)
      27           0 : #define VIM_INFO            (VIM_BASE_ADDR + 0x0004)
      28           0 : #define VIM_PRIIRQ          (VIM_BASE_ADDR + 0x0008)
      29           0 : #define VIM_PRIFIQ          (VIM_BASE_ADDR + 0x000C)
      30           0 : #define VIM_IRQGSTS         (VIM_BASE_ADDR + 0x0010)
      31           0 : #define VIM_FIQGSTS         (VIM_BASE_ADDR + 0x0014)
      32           0 : #define VIM_IRQVEC          (VIM_BASE_ADDR + 0x0018)
      33           0 : #define VIM_FIQVEC          (VIM_BASE_ADDR + 0x001C)
      34           0 : #define VIM_ACTIRQ          (VIM_BASE_ADDR + 0x0020)
      35           0 : #define VIM_ACTFIQ          (VIM_BASE_ADDR + 0x0024)
      36           0 : #define VIM_DEDVEC          (VIM_BASE_ADDR + 0x0030)
      37             : 
      38           0 : #define VIM_RAW(n)          (VIM_BASE_ADDR + (0x400) + ((n) * 0x20))
      39           0 : #define VIM_STS(n)          (VIM_BASE_ADDR + (0x404) + ((n) * 0x20))
      40           0 : #define VIM_INTR_EN_SET(n)  (VIM_BASE_ADDR + (0x408) + ((n) * 0x20))
      41           0 : #define VIM_INTR_EN_CLR(n)  (VIM_BASE_ADDR + (0x40c) + ((n) * 0x20))
      42           0 : #define VIM_IRQSTS(n)       (VIM_BASE_ADDR + (0x410) + ((n) * 0x20))
      43           0 : #define VIM_FIQSTS(n)       (VIM_BASE_ADDR + (0x414) + ((n) * 0x20))
      44           0 : #define VIM_INTMAP(n)       (VIM_BASE_ADDR + (0x418) + ((n) * 0x20))
      45           0 : #define VIM_INTTYPE(n)      (VIM_BASE_ADDR + (0x41c) + ((n) * 0x20))
      46           0 : #define VIM_PRI_INT(n)      (VIM_BASE_ADDR + (0x1000) + ((n) * 0x4))
      47           0 : #define VIM_VEC_INT(n)      (VIM_BASE_ADDR + (0x2000) + ((n) * 0x4))
      48             : 
      49             : /* RAW */
      50             : 
      51           0 : #define VIM_GRP_RAW_STS_MASK                 (BIT_MASK(32))
      52           0 : #define VIM_GRP_RAW_STS_SHIFT                (0x00000000U)
      53           0 : #define VIM_GRP_RAW_STS_RESETVAL             (0x00000000U)
      54           0 : #define VIM_GRP_RAW_STS_MAX                  (BIT_MASK(32))
      55             : 
      56           0 : #define VIM_GRP_RAW_RESETVAL                 (0x00000000U)
      57             : 
      58             : /* STS */
      59             : 
      60           0 : #define VIM_GRP_STS_MSK_MASK                 (BIT_MASK(32))
      61           0 : #define VIM_GRP_STS_MSK_SHIFT                (0x00000000U)
      62           0 : #define VIM_GRP_STS_MSK_RESETVAL             (0x00000000U)
      63           0 : #define VIM_GRP_STS_MSK_MAX                  (BIT_MASK(32))
      64             : 
      65           0 : #define VIM_GRP_STS_RESETVAL                 (0x00000000U)
      66             : 
      67             : /* INTR_EN_SET */
      68             : 
      69           0 : #define VIM_GRP_INTR_EN_SET_MSK_MASK         (BIT_MASK(32))
      70           0 : #define VIM_GRP_INTR_EN_SET_MSK_SHIFT        (0x00000000U)
      71           0 : #define VIM_GRP_INTR_EN_SET_MSK_RESETVAL     (0x00000000U)
      72           0 : #define VIM_GRP_INTR_EN_SET_MSK_MAX          (BIT_MASK(32))
      73             : 
      74           0 : #define VIM_GRP_INTR_EN_SET_RESETVAL         (0x00000000U)
      75             : 
      76             : /* INTR_EN_CLR */
      77             : 
      78           0 : #define VIM_GRP_INTR_EN_CLR_MSK_MASK         (BIT_MASK(32))
      79           0 : #define VIM_GRP_INTR_EN_CLR_MSK_SHIFT        (0x00000000U)
      80           0 : #define VIM_GRP_INTR_EN_CLR_MSK_RESETVAL     (0x00000000U)
      81           0 : #define VIM_GRP_INTR_EN_CLR_MSK_MAX          (BIT_MASK(32))
      82             : 
      83           0 : #define VIM_GRP_INTR_EN_CLR_RESETVAL         (0x00000000U)
      84             : 
      85             : /* IRQSTS */
      86             : 
      87           0 : #define VIM_GRP_IRQSTS_MSK_MASK              (BIT_MASK(32))
      88           0 : #define VIM_GRP_IRQSTS_MSK_SHIFT             (0x00000000U)
      89           0 : #define VIM_GRP_IRQSTS_MSK_RESETVAL          (0x00000000U)
      90           0 : #define VIM_GRP_IRQSTS_MSK_MAX               (BIT_MASK(32))
      91             : 
      92           0 : #define VIM_GRP_IRQSTS_RESETVAL              (0x00000000U)
      93             : 
      94             : /* FIQSTS */
      95             : 
      96           0 : #define VIM_GRP_FIQSTS_MSK_MASK              (BIT_MASK(32))
      97           0 : #define VIM_GRP_FIQSTS_MSK_SHIFT             (0x00000000U)
      98           0 : #define VIM_GRP_FIQSTS_MSK_RESETVAL          (0x00000000U)
      99           0 : #define VIM_GRP_FIQSTS_MSK_MAX               (BIT_MASK(32))
     100             : 
     101           0 : #define VIM_GRP_FIQSTS_RESETVAL              (0x00000000U)
     102             : 
     103             : /* INTMAP */
     104             : 
     105           0 : #define VIM_GRP_INTMAP_MSK_MASK              (BIT_MASK(32))
     106           0 : #define VIM_GRP_INTMAP_MSK_SHIFT             (0x00000000U)
     107           0 : #define VIM_GRP_INTMAP_MSK_RESETVAL          (0x00000000U)
     108           0 : #define VIM_GRP_INTMAP_MSK_MAX               (BIT_MASK(32))
     109             : 
     110           0 : #define VIM_GRP_INTMAP_RESETVAL              (0x00000000U)
     111             : 
     112             : /* INTTYPE */
     113             : 
     114           0 : #define VIM_GRP_INTTYPE_MSK_MASK             (BIT_MASK(32))
     115           0 : #define VIM_GRP_INTTYPE_MSK_SHIFT            (0x00000000U)
     116           0 : #define VIM_GRP_INTTYPE_MSK_RESETVAL         (0x00000000U)
     117           0 : #define VIM_GRP_INTTYPE_MSK_MAX              (BIT_MASK(32))
     118             : 
     119           0 : #define VIM_GRP_INTTYPE_RESETVAL             (0x00000000U)
     120             : 
     121             : /* INT */
     122             : 
     123           0 : #define VIM_PRI_INT_VAL_MASK                 (BIT_MASK(4))
     124           0 : #define VIM_PRI_INT_VAL_SHIFT                (0x00000000U)
     125           0 : #define VIM_PRI_INT_VAL_RESETVAL             (BIT_MASK(4))
     126           0 : #define VIM_PRI_INT_VAL_MAX                  (BIT_MASK(4))
     127             : 
     128           0 : #define VIM_PRI_INT_RESETVAL                 (BIT_MASK(4))
     129             : 
     130             : /* INT */
     131             : 
     132           0 : #define VIM_VEC_INT_VAL_MASK                 (0xFFFFFFFCU)
     133           0 : #define VIM_VEC_INT_VAL_SHIFT                (0x00000002U)
     134           0 : #define VIM_VEC_INT_VAL_RESETVAL             (0x00000000U)
     135           0 : #define VIM_VEC_INT_VAL_MAX                  (BIT_MASK(30))
     136             : 
     137           0 : #define VIM_VEC_INT_RESETVAL                 (0x00000000U)
     138             : 
     139             : /* INFO */
     140             : 
     141           0 : #define VIM_INFO_INTERRUPTS_MASK             (BIT_MASK(11))
     142           0 : #define VIM_INFO_INTERRUPTS_SHIFT            (0x00000000U)
     143           0 : #define VIM_INFO_INTERRUPTS_RESETVAL         (0x00000400U)
     144           0 : #define VIM_INFO_INTERRUPTS_MAX              (BIT_MASK(11))
     145             : 
     146           0 : #define VIM_INFO_RESETVAL                    (0x00000400U)
     147             : 
     148             : /* PRIIRQ */
     149             : 
     150           0 : #define VIM_PRIIRQ_VALID_MASK                (0x80000000U)
     151           0 : #define VIM_PRIIRQ_VALID_SHIFT               (BIT_MASK(5))
     152           0 : #define VIM_PRIIRQ_VALID_RESETVAL            (0x00000000U)
     153           0 : #define VIM_PRIIRQ_VALID_MAX                 (0x00000001U)
     154             : 
     155           0 : #define VIM_PRIIRQ_VALID_VAL_TRUE            (0x1U)
     156           0 : #define VIM_PRIIRQ_VALID_VAL_FALSE           (0x0U)
     157             : 
     158           0 : #define VIM_PRIIRQ_PRI_MASK                  (0x000F0000U)
     159           0 : #define VIM_PRIIRQ_PRI_SHIFT                 (0x00000010U)
     160           0 : #define VIM_PRIIRQ_PRI_RESETVAL              (0x00000000U)
     161           0 : #define VIM_PRIIRQ_PRI_MAX                   (BIT_MASK(4))
     162             : 
     163           0 : #define VIM_PRIIRQ_NUM_MASK                  (BIT_MASK(10))
     164           0 : #define VIM_PRIIRQ_NUM_SHIFT                 (0x00000000U)
     165           0 : #define VIM_PRIIRQ_NUM_RESETVAL              (0x00000000U)
     166           0 : #define VIM_PRIIRQ_NUM_MAX                   (BIT_MASK(10))
     167             : 
     168           0 : #define VIM_PRIIRQ_RESETVAL                  (0x00000000U)
     169             : 
     170             : /* PRIFIQ */
     171             : 
     172           0 : #define VIM_PRIFIQ_VALID_MASK                (0x80000000U)
     173           0 : #define VIM_PRIFIQ_VALID_SHIFT               (BIT_MASK(5))
     174           0 : #define VIM_PRIFIQ_VALID_RESETVAL            (0x00000000U)
     175           0 : #define VIM_PRIFIQ_VALID_MAX                 (0x00000001U)
     176             : 
     177           0 : #define VIM_PRIFIQ_VALID_VAL_TRUE            (0x1U)
     178           0 : #define VIM_PRIFIQ_VALID_VAL_FALSE           (0x0U)
     179             : 
     180           0 : #define VIM_PRIFIQ_PRI_MASK                  (0x000F0000U)
     181           0 : #define VIM_PRIFIQ_PRI_SHIFT                 (0x00000010U)
     182           0 : #define VIM_PRIFIQ_PRI_RESETVAL              (0x00000000U)
     183           0 : #define VIM_PRIFIQ_PRI_MAX                   (BIT_MASK(4))
     184             : 
     185           0 : #define VIM_PRIFIQ_NUM_MASK                  (BIT_MASK(10))
     186           0 : #define VIM_PRIFIQ_NUM_SHIFT                 (0x00000000U)
     187           0 : #define VIM_PRIFIQ_NUM_RESETVAL              (0x00000000U)
     188           0 : #define VIM_PRIFIQ_NUM_MAX                   (BIT_MASK(10))
     189             : 
     190           0 : #define VIM_PRIFIQ_RESETVAL                  (0x00000000U)
     191             : 
     192             : /* IRQGSTS */
     193             : 
     194           0 : #define VIM_IRQGSTS_STS_MASK                 (BIT_MASK(32))
     195           0 : #define VIM_IRQGSTS_STS_SHIFT                (0x00000000U)
     196           0 : #define VIM_IRQGSTS_STS_RESETVAL             (0x00000000U)
     197           0 : #define VIM_IRQGSTS_STS_MAX                  (BIT_MASK(32))
     198             : 
     199           0 : #define VIM_IRQGSTS_RESETVAL                 (0x00000000U)
     200             : 
     201             : /* FIQGSTS */
     202             : 
     203           0 : #define VIM_FIQGSTS_STS_MASK                 (BIT_MASK(32))
     204           0 : #define VIM_FIQGSTS_STS_SHIFT                (0x00000000U)
     205           0 : #define VIM_FIQGSTS_STS_RESETVAL             (0x00000000U)
     206           0 : #define VIM_FIQGSTS_STS_MAX                  (BIT_MASK(32))
     207             : 
     208           0 : #define VIM_FIQGSTS_RESETVAL                 (0x00000000U)
     209             : 
     210             : /* IRQVEC */
     211             : 
     212           0 : #define VIM_IRQVEC_ADDR_MASK                 (0xFFFFFFFCU)
     213           0 : #define VIM_IRQVEC_ADDR_SHIFT                (0x00000002U)
     214           0 : #define VIM_IRQVEC_ADDR_RESETVAL             (0x00000000U)
     215           0 : #define VIM_IRQVEC_ADDR_MAX                  (BIT_MASK(30))
     216             : 
     217           0 : #define VIM_IRQVEC_RESETVAL                  (0x00000000U)
     218             : 
     219             : /* FIQVEC */
     220             : 
     221           0 : #define VIM_FIQVEC_ADDR_MASK                 (0xFFFFFFFCU)
     222           0 : #define VIM_FIQVEC_ADDR_SHIFT                (0x00000002U)
     223           0 : #define VIM_FIQVEC_ADDR_RESETVAL             (0x00000000U)
     224           0 : #define VIM_FIQVEC_ADDR_MAX                  (BIT_MASK(30))
     225             : 
     226           0 : #define VIM_FIQVEC_RESETVAL                  (0x00000000U)
     227             : 
     228             : /* ACTIRQ */
     229             : 
     230           0 : #define VIM_ACTIRQ_VALID_MASK                (0x80000000U)
     231           0 : #define VIM_ACTIRQ_VALID_SHIFT               (BIT_MASK(5))
     232           0 : #define VIM_ACTIRQ_VALID_RESETVAL            (0x00000000U)
     233           0 : #define VIM_ACTIRQ_VALID_MAX                 (0x00000001U)
     234             : 
     235           0 : #define VIM_ACTIRQ_VALID_VAL_TRUE            (0x1U)
     236           0 : #define VIM_ACTIRQ_VALID_VAL_FALSE           (0x0U)
     237             : 
     238           0 : #define VIM_ACTIRQ_PRI_MASK                  (0x000F0000U)
     239           0 : #define VIM_ACTIRQ_PRI_SHIFT                 (0x00000010U)
     240           0 : #define VIM_ACTIRQ_PRI_RESETVAL              (0x00000000U)
     241           0 : #define VIM_ACTIRQ_PRI_MAX                   (BIT_MASK(4))
     242             : 
     243           0 : #define VIM_ACTIRQ_NUM_MASK                  (BIT_MASK(10))
     244           0 : #define VIM_ACTIRQ_NUM_SHIFT                 (0x00000000U)
     245           0 : #define VIM_ACTIRQ_NUM_RESETVAL              (0x00000000U)
     246           0 : #define VIM_ACTIRQ_NUM_MAX                   (BIT_MASK(10))
     247             : 
     248           0 : #define VIM_ACTIRQ_RESETVAL                  (0x00000000U)
     249             : 
     250             : /* ACTFIQ */
     251             : 
     252           0 : #define VIM_ACTFIQ_VALID_MASK                (0x80000000U)
     253           0 : #define VIM_ACTFIQ_VALID_SHIFT               (BIT_MASK(5))
     254           0 : #define VIM_ACTFIQ_VALID_RESETVAL            (0x00000000U)
     255           0 : #define VIM_ACTFIQ_VALID_MAX                 (0x00000001U)
     256             : 
     257           0 : #define VIM_ACTFIQ_VALID_VAL_TRUE            (0x1U)
     258           0 : #define VIM_ACTFIQ_VALID_VAL_FALSE           (0x0U)
     259             : 
     260           0 : #define VIM_ACTFIQ_PRI_MASK                  (0x000F0000U)
     261           0 : #define VIM_ACTFIQ_PRI_SHIFT                 (0x00000010U)
     262           0 : #define VIM_ACTFIQ_PRI_RESETVAL              (0x00000000U)
     263           0 : #define VIM_ACTFIQ_PRI_MAX                   (BIT_MASK(4))
     264             : 
     265           0 : #define VIM_ACTFIQ_NUM_MASK                  (BIT_MASK(10))
     266           0 : #define VIM_ACTFIQ_NUM_SHIFT                 (0x00000000U)
     267           0 : #define VIM_ACTFIQ_NUM_RESETVAL              (0x00000000U)
     268           0 : #define VIM_ACTFIQ_NUM_MAX                   (BIT_MASK(10))
     269             : 
     270           0 : #define VIM_ACTFIQ_RESETVAL                  (0x00000000U)
     271             : 
     272             : /* DEDVEC */
     273             : 
     274           0 : #define VIM_DEDVEC_ADDR_MASK                 (0xFFFFFFFCU)
     275           0 : #define VIM_DEDVEC_ADDR_SHIFT                (0x00000002U)
     276           0 : #define VIM_DEDVEC_ADDR_RESETVAL             (0x00000000U)
     277           0 : #define VIM_DEDVEC_ADDR_MAX                  (BIT_MASK(30))
     278             : 
     279           0 : #define VIM_DEDVEC_RESETVAL                  (0x00000000U)
     280             : 
     281             : /*
     282             :  * VIM Driver Interface Functions
     283             :  */
     284             : 
     285             : /**
     286             :  * @brief Get active interrupt ID.
     287             :  *
     288             :  * @return Returns the ID of an active interrupt.
     289             :  */
     290             : unsigned int z_vim_irq_get_active(void);
     291             : 
     292             : /**
     293             :  * @brief Signal end-of-interrupt.
     294             :  *
     295             :  * @param irq interrupt ID.
     296             :  */
     297             : void z_vim_irq_eoi(unsigned int irq);
     298             : 
     299             : /**
     300             :  * @brief Interrupt controller initialization.
     301             :  */
     302             : void z_vim_irq_init(void);
     303             : 
     304             : /**
     305             :  * @brief Configure priority, irq type for the interrupt ID.
     306             :  *
     307             :  * @param irq interrupt ID.
     308             :  * @param prio interrupt priority.
     309             :  * @param flags interrupt flags.
     310             :  */
     311             : void z_vim_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags);
     312             : 
     313             : /**
     314             :  * @brief Enable Interrupt.
     315             :  *
     316             :  * @param irq interrupt ID.
     317             :  */
     318             : void z_vim_irq_enable(unsigned int irq);
     319             : 
     320             : /**
     321             :  * @brief Disable Interrupt.
     322             :  *
     323             :  * @param irq interrupt ID.
     324             :  */
     325             : void z_vim_irq_disable(unsigned int irq);
     326             : 
     327             : /**
     328             :  * @brief Check if an interrupt is enabled.
     329             :  *
     330             :  * @param irq interrupt ID.
     331             :  *
     332             :  * @retval 0 If interrupt is disabled.
     333             :  * @retval 1 If interrupt is enabled.
     334             :  */
     335             : int z_vim_irq_is_enabled(unsigned int irq);
     336             : 
     337             : /**
     338             :  * @brief Raise a software interrupt.
     339             :  *
     340             :  * @param irq interrupt ID.
     341             :  */
     342             : void z_vim_arm_enter_irq(int irq);
     343             : 
     344             : #endif /* ZEPHYR_DRIVERS_INTC_VIM_H_ */