Line data    Source code

       1            1 : /*
       2              :  * Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : /**
       8              :  * @file
       9              :  * @brief Driver for Platform Level Interrupt Controller (PLIC)
      10              :  */
      11              : 
      12              : #ifndef ZEPHYR_INCLUDE_DRIVERS_RISCV_PLIC_H_
      13              : #define ZEPHYR_INCLUDE_DRIVERS_RISCV_PLIC_H_
      14              : 
      15              : #include <zephyr/device.h>
      16              : 
      17              : /**
      18              :  * @brief Enable interrupt
      19              :  *
      20              :  * @param irq Multi-level encoded interrupt ID
      21              :  */
      22            1 : void riscv_plic_irq_enable(uint32_t irq);
      23              : 
      24              : /**
      25              :  * @brief Disable interrupt
      26              :  *
      27              :  * @param irq Multi-level encoded interrupt ID
      28              :  */
      29            1 : void riscv_plic_irq_disable(uint32_t irq);
      30              : 
      31              : /**
      32              :  * @brief Check if an interrupt is enabled
      33              :  *
      34              :  * @param irq Multi-level encoded interrupt ID
      35              :  * @return Returns true if interrupt is enabled, false otherwise
      36              :  */
      37            1 : int riscv_plic_irq_is_enabled(uint32_t irq);
      38              : 
      39              : /**
      40              :  * @brief Set interrupt priority
      41              :  *
      42              :  * @param irq Multi-level encoded interrupt ID
      43              :  * @param prio interrupt priority
      44              :  */
      45            1 : void riscv_plic_set_priority(uint32_t irq, uint32_t prio);
      46              : 
      47              : /**
      48              :  * @brief Set IRQ affinity.
      49              :  *
      50              :  * @param irq IRQ line.
      51              :  * @param cpumask CPU bit mask.
      52              :  *
      53              :  * @return 0 if success, negative errno value otherwise
      54              :  */
      55            1 : int riscv_plic_irq_set_affinity(uint32_t irq, uint32_t cpumask);
      56              : 
      57              : /**
      58              :  * @brief Set interrupt as pending
      59              :  *
      60              :  * @param irq Multi-level encoded interrupt ID
      61              :  */
      62            1 : void riscv_plic_irq_set_pending(uint32_t irq);
      63              : 
      64              : /**
      65              :  * @brief Get active interrupt ID
      66              :  *
      67              :  * @note Should be called with interrupt locked
      68              :  *
      69              :  * @return Returns the ID of an active interrupt
      70              :  */
      71            1 : unsigned int riscv_plic_get_irq(void);
      72              : 
      73              : /**
      74              :  * @brief Get active interrupt controller device
      75              :  *
      76              :  * @note Should be called with interrupt locked
      77              :  *
      78              :  * @return Returns device pointer of the active interrupt device
      79              :  */
      80            1 : const struct device *riscv_plic_get_dev(void);
      81              : 
      82              : #endif /* ZEPHYR_INCLUDE_DRIVERS_RISCV_PLIC_H_ */