Line data Source code
1 0 : /*
2 : * Copyright (c) 2024 Analog Devices Inc.
3 : * Copyright (c) 2024 Baylibre SAS
4 : *
5 : * SPDX-License-Identifier: Apache-2.0
6 : */
7 :
8 : #ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_MAX22017_H_
9 : #define ZEPHYR_INCLUDE_DRIVERS_MFD_MAX22017_H_
10 :
11 : #include <zephyr/device.h>
12 :
13 0 : #define MAX22017_LDAC_TOGGLE_TIME 200
14 0 : #define MAX22017_MAX_CHANNEL 2
15 0 : #define MAX22017_CRC_POLY 0x8c /* reversed 0x31 poly for crc8-maxim */
16 :
17 0 : #define MAX22017_GEN_ID_OFF 0x00
18 0 : #define MAX22017_GEN_ID_PROD_ID GENMASK(15, 8)
19 0 : #define MAX22017_GEN_ID_REV_ID GENMASK(7, 0)
20 :
21 0 : #define MAX22017_GEN_SERIAL_MSB_OFF 0x01
22 0 : #define MAX22017_GEN_SERIAL_MSB_SERIAL_MSB GENMASK(15, 0)
23 :
24 0 : #define MAX22017_GEN_SERIAL_LSB_OFF 0x02
25 0 : #define MAX22017_GEN_SERIAL_LSB_SERIAL_LSB GENMASK(15, 0)
26 :
27 0 : #define MAX22017_GEN_CNFG_OFF 0x03
28 0 : #define MAX22017_GEN_CNFG_OPENWIRE_DTCT_CNFG GENMASK(15, 14)
29 0 : #define MAX22017_GEN_CNFG_TMOUT_SEL GENMASK(13, 10)
30 0 : #define MAX22017_GEN_CNFG_TMOUT_CNFG BIT(9)
31 0 : #define MAX22017_GEN_CNFG_TMOUT_EN BIT(8)
32 0 : #define MAX22017_GEN_CNFG_THSHDN_CNFG GENMASK(7, 6)
33 0 : #define MAX22017_GEN_CNFG_OVC_SHDN_CNFG GENMASK(5, 4)
34 0 : #define MAX22017_GEN_CNFG_OVC_CNFG GENMASK(3, 2)
35 0 : #define MAX22017_GEN_CNFG_CRC_EN BIT(1)
36 0 : #define MAX22017_GEN_CNFG_DACREF_SEL BIT(0)
37 :
38 0 : #define MAX22017_GEN_GPIO_CTRL_OFF 0x04
39 0 : #define MAX22017_GEN_GPIO_CTRL_GPIO_EN GENMASK(13, 8)
40 0 : #define MAX22017_GEN_GPIO_CTRL_GPIO_DIR GENMASK(5, 0)
41 :
42 0 : #define MAX22017_GEN_GPIO_DATA_OFF 0x05
43 0 : #define MAX22017_GEN_GPIO_DATA_GPO_DATA GENMASK(13, 8)
44 0 : #define MAX22017_GEN_GPIO_DATA_GPI_DATA GENMASK(5, 0)
45 :
46 0 : #define MAX22017_GEN_GPI_INT_OFF 0x06
47 0 : #define MAX22017_GEN_GPI_INT_GPI_POS_EDGE_INT GENMASK(13, 8)
48 0 : #define MAX22017_GEN_GPI_INT_GPI_NEG_EDGE_INT GENMASK(5, 0)
49 :
50 0 : #define MAX22017_GEN_GPI_INT_STA_OFF 0x07
51 0 : #define MAX22017_GEN_GPI_INT_STA_GPI_POS_EDGE_INT_STA GENMASK(13, 8)
52 0 : #define MAX22017_GEN_GPI_INT_STA_GPI_NEG_EDGE_INT_STA GENMASK(5, 0)
53 :
54 0 : #define MAX22017_GEN_INT_OFF 0x08
55 0 : #define MAX22017_GEN_INT_FAIL_INT BIT(15)
56 0 : #define MAX22017_GEN_INT_CONV_OVF_INT GENMASK(13, 12)
57 0 : #define MAX22017_GEN_INT_OPENWIRE_DTCT_INT GENMASK(11, 10)
58 0 : #define MAX22017_GEN_INT_HVDD_INT BIT(9)
59 0 : #define MAX22017_GEN_INT_TMOUT_INT BIT(8)
60 0 : #define MAX22017_GEN_INT_THSHDN_INT GENMASK(7, 6)
61 0 : #define MAX22017_GEN_INT_THWRNG_INT GENMASK(5, 4)
62 0 : #define MAX22017_GEN_INT_OVC_INT GENMASK(3, 2)
63 0 : #define MAX22017_GEN_INT_CRC_INT BIT(1)
64 0 : #define MAX22017_GEN_INT_GPI_INT BIT(0)
65 :
66 0 : #define MAX22017_GEN_INTEN_OFF 0x09
67 0 : #define MAX22017_GEN_INTEN_CONV_OVF_INTEN GENMASK(13, 12)
68 0 : #define MAX22017_GEN_INTEN_OPENWIRE_DTCT_INTEN GENMASK(11, 10)
69 0 : #define MAX22017_GEN_INTEN_HVDD_INTEN BIT(9)
70 0 : #define MAX22017_GEN_INTEN_TMOUT_INTEN BIT(8)
71 0 : #define MAX22017_GEN_INTEN_THSHDN_INTEN GENMASK(7, 6)
72 0 : #define MAX22017_GEN_INTEN_THWRNG_INTEN GENMASK(5, 4)
73 0 : #define MAX22017_GEN_INTEN_OVC_INTEN GENMASK(3, 2)
74 0 : #define MAX22017_GEN_INTEN_CRC_INTEN BIT(1)
75 0 : #define MAX22017_GEN_INTEN_GPI_INTEN BIT(0)
76 :
77 0 : #define MAX22017_GEN_RST_CTRL_OFF 0x0A
78 0 : #define MAX22017_GEN_RST_CTRL_AO_COEFF_RELOAD GENMASK(15, 14)
79 0 : #define MAX22017_GEN_RST_CTRL_GEN_RST BIT(9)
80 :
81 0 : #define MAX22017_AO_CMD_OFF 0x40
82 0 : #define MAX22017_AO_CMD_AO_LD_CTRL GENMASK(15, 14)
83 :
84 0 : #define MAX22017_AO_STA_OFF 0x41
85 0 : #define MAX22017_AO_STA_BUSY_STA GENMASK(15, 14)
86 0 : #define MAX22017_AO_STA_SLEW_STA GENMASK(13, 12)
87 0 : #define MAX22017_AO_STA_FAIL_STA BIT(0)
88 :
89 0 : #define MAX22017_AO_CNFG_OFF 0x42
90 0 : #define MAX22017_AO_CNFG_AO_LD_CNFG GENMASK(15, 14)
91 0 : #define MAX22017_AO_CNFG_AO_CM_SENSE GENMASK(13, 12)
92 0 : #define MAX22017_AO_CNFG_AO_UNI GENMASK(11, 10)
93 0 : #define MAX22017_AO_CNFG_AO_MODE GENMASK(9, 8)
94 0 : #define MAX22017_AO_CNFG_AO_OPENWIRE_DTCT_LMT GENMASK(5, 4)
95 0 : #define MAX22017_AO_CNFG_AI_EN GENMASK(3, 2)
96 0 : #define MAX22017_AO_CNFG_AO_EN GENMASK(1, 0)
97 :
98 0 : #define MAX22017_AO_SLEW_RATE_CHn_OFF(n) (0x43 + n)
99 0 : #define MAX22017_AO_SLEW_RATE_CHn_AO_SR_EN_CHn BIT(5)
100 0 : #define MAX22017_AO_SLEW_RATE_CHn_AO_SR_SEL_CHn BIT(4)
101 0 : #define MAX22017_AO_SLEW_RATE_CHn_AO_SR_STEP_SIZE_CHn GENMASK(3, 2)
102 0 : #define MAX22017_AO_SLEW_RATE_CHn_AO_SR_UPDATE_RATE_CHn GENMASK(1, 0)
103 :
104 0 : #define MAX22017_AO_DATA_CHn_OFF(n) (0x45 + n)
105 0 : #define MAX22017_AO_DATA_CHn_AO_DATA_CH GENMASK(15, 0)
106 :
107 0 : #define MAX22017_AO_OFFSET_CORR_CHn_OFF(n) (0x47 + (2 * n))
108 0 : #define MAX22017_AO_OFFSET_CORR_CHn_AO_OFFSET_CH GENMASK(15, 0)
109 :
110 0 : #define MAX22017_AO_GAIN_CORR_CHn_OFF(n) (0x48 + (2 * n))
111 0 : #define MAX22017_AO_GAIN_CORR_CHn_AO_GAIN_CH GENMASK(15, 0)
112 :
113 0 : #define MAX22017_SPI_TRANS_ADDR GENMASK(7, 1)
114 0 : #define MAX22017_SPI_TRANS_DIR BIT(0)
115 0 : #define MAX22017_SPI_TRANS_PAYLOAD GENMASK(15, 0)
116 :
117 : /**
118 : * @defgroup mdf_interface_max22017 MFD MAX22017 interface
119 : * @ingroup mfd_interfaces
120 : * @{
121 : */
122 :
123 : /**
124 : * @brief Read register from max22017
125 : *
126 : * @param dev max22017 mfd device
127 : * @param addr register address to read from
128 : * @param value pointer to buffer for received data
129 : * @retval 0 If successful
130 : * @retval -errno In case of any error (see spi_transceive_dt())
131 : */
132 1 : int max22017_reg_read(const struct device *dev, uint8_t addr, uint16_t *value);
133 :
134 : /**
135 : * @brief Write register to max22017
136 : *
137 : * @param dev max22017 mfd device
138 : * @param addr register address to write to
139 : * @param value content to write
140 : * @retval 0 If successful
141 : * @retval -errno In case of any error (see spi_write_dt())
142 : */
143 1 : int max22017_reg_write(const struct device *dev, uint8_t addr, uint16_t value);
144 :
145 : /**
146 : * @}
147 : */
148 :
149 0 : struct max22017_data {
150 0 : const struct device *dev;
151 0 : struct k_mutex lock;
152 0 : struct k_work int_work;
153 0 : struct gpio_callback callback_int;
154 0 : bool crc_enabled;
155 : #ifdef CONFIG_GPIO_MAX22017
156 : sys_slist_t callbacks_gpi;
157 : #endif
158 : };
159 :
160 : #endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_MAX22017_H_ */
|
