Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Renesas Electronics Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_DRIVERS_MISC_RENESAS_RX_DTC_H_
8 : #define ZEPHYR_DRIVERS_MISC_RENESAS_RX_DTC_H_
9 :
10 : #include <zephyr/drivers/gpio.h>
11 0 : #define DTC_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__))
12 0 : #define DTC_ALIGN_VARIABLE(x) __aligned(x)
13 0 : #define DTC_SECTION_ATTRIBUTE DTC_PLACE_IN_SECTION(".dtc_vector_table")
14 :
15 0 : #define DTC_VECTOR_TABLE_ENTRIES (CONFIG_NUM_IRQS)
16 0 : #define DTC_PRV_ACT_BIT_MASK (1 << 15) /* DTC Active flag (DTCSTS.ACT) bit mask */
17 0 : #define DTC_PRV_VECT_NR_MASK (0x00FF) /* DTC-Activating Vector Number bits mask */
18 : /* Counter Register A Lower Byte Mask */
19 0 : #define DTC_PRV_MASK_CRAL (0xFFU)
20 : /* Counter Register A Upper Byte Offset */
21 0 : #define DTC_PRV_OFFSET_CRAH (8U)
22 : /* Max configurable number of transfers in NORMAL MODE */
23 0 : #define DTC_MAX_NORMAL_TRANSFER_LENGTH (0x10000)
24 : /* Max number of transfers per repeat for REPEAT MODE */
25 0 : #define DTC_MAX_REPEAT_TRANSFER_LENGTH (0x100)
26 : /* Max number of transfers per block in BLOCK MODE */
27 0 : #define DTC_MAX_BLOCK_TRANSFER_LENGTH (0x100)
28 : /* Max configurable number of blocks to transfer in BLOCK MODE */
29 0 : #define DTC_MAX_BLOCK_COUNT (0x10000)
30 :
31 0 : typedef enum e_transfer_addr_mode {
32 : TRANSFER_ADDR_MODE_FIXED = 0,
33 : TRANSFER_ADDR_MODE_OFFSET = 1,
34 : TRANSFER_ADDR_MODE_INCREMENTED = 2,
35 : TRANSFER_ADDR_MODE_DECREMENTED = 3
36 0 : } transfer_addr_mode_t;
37 :
38 0 : typedef enum e_transfer_repeat_area {
39 : TRANSFER_REPEAT_AREA_DESTINATION = 0,
40 : TRANSFER_REPEAT_AREA_SOURCE = 1
41 0 : } transfer_repeat_area_t;
42 :
43 0 : typedef enum e_transfer_irq {
44 : TRANSFER_IRQ_END = 0,
45 : TRANSFER_IRQ_EACH = 1
46 0 : } transfer_irq_t;
47 :
48 0 : typedef enum e_transfer_chain_mode {
49 : TRANSFER_CHAIN_MODE_DISABLED = 0,
50 : TRANSFER_CHAIN_MODE_EACH = 2,
51 : TRANSFER_CHAIN_MODE_END = 3
52 0 : } transfer_chain_mode_t;
53 :
54 0 : typedef enum e_transfer_size {
55 : TRANSFER_SIZE_1_BYTE = 0,
56 : TRANSFER_SIZE_2_BYTE = 1,
57 : TRANSFER_SIZE_4_BYTE = 2
58 0 : } transfer_size_t;
59 :
60 0 : typedef enum e_transfer_mode {
61 : TRANSFER_MODE_NORMAL = 0,
62 : TRANSFER_MODE_REPEAT = 1,
63 : TRANSFER_MODE_BLOCK = 2,
64 : TRANSFER_MODE_REPEAT_BLOCK = 3
65 0 : } transfer_mode_t;
66 :
67 0 : typedef enum e_dtc_act_status {
68 : DTC_ACT_IDLE = 0,
69 : DTC_ACT_CONFIGURED = 1,
70 : DTC_ACT_IN_PROGRESS = 2,
71 0 : } dtc_act_status_t;
72 :
73 0 : typedef struct st_transfer_info {
74 : union {
75 : struct {
76 0 : unsigned int: 16;
77 : unsigned int: 2;
78 :
79 0 : transfer_addr_mode_t dest_addr_mode: 2;
80 :
81 0 : transfer_repeat_area_t repeat_area: 1;
82 :
83 0 : transfer_irq_t irq: 1;
84 :
85 0 : transfer_chain_mode_t chain_mode: 2;
86 :
87 : unsigned int: 2;
88 :
89 0 : transfer_addr_mode_t src_addr_mode: 2;
90 :
91 0 : transfer_size_t size: 2;
92 :
93 0 : transfer_mode_t mode: 2;
94 0 : } transfer_settings_word_b;
95 :
96 0 : uint32_t transfer_settings_word;
97 0 : };
98 :
99 0 : void const *volatile p_src;
100 0 : void *volatile p_dest;
101 :
102 0 : volatile uint16_t num_blocks;
103 :
104 0 : volatile uint16_t length;
105 0 : } transfer_info_t;
106 :
107 0 : typedef struct st_transfer_properties {
108 0 : uint32_t block_count_max; /* Maximum number of blocks */
109 0 : uint32_t block_count_remaining; /* Number of blocks remaining */
110 0 : uint32_t transfer_length_max; /* Maximum number of transfers */
111 0 : uint32_t transfer_length_remaining; /* Number of transfers remaining */
112 0 : } transfer_properties_t;
113 :
114 0 : struct dtc_transfer_status {
115 0 : uint8_t activation_irq;
116 0 : bool in_progress;
117 : };
118 :
119 : /**
120 : * @brief Turn off module DTC.
121 : * @param dev DTC device instance.
122 : *
123 : * @retval 0 On success.
124 : */
125 1 : int dtc_renesas_rx_off(const struct device *dev);
126 :
127 : /**
128 : * @brief Turn on module DTC.
129 : * @param dev DTC device instance.
130 : *
131 : * @retval 0 On success.
132 : */
133 1 : int dtc_renesas_rx_on(const struct device *dev);
134 :
135 : /**
136 : * @brief Configure the p_info state and write p_info to DTC vector table.
137 : *
138 : * @param dev DTC device instance.
139 : * @param activation_irq activation source.
140 : * @param p_info transfer info.
141 : *
142 : * @retval 0 On success.
143 : * @retval -EINVAL if activation source is invalid.
144 : */
145 1 : int dtc_renesas_rx_configuration(const struct device *dev, uint8_t activation_irq,
146 : transfer_info_t *p_info);
147 :
148 : /**
149 : * @brief Enable transfer in ICU on this activation source.
150 : *
151 : * @param activation_irq activation source.
152 : *
153 : * @retval 0 On success.
154 : * @retval -EINVAL if activation source is invalid.
155 : */
156 1 : int dtc_renesas_rx_enable_transfer(uint8_t activation_irq);
157 :
158 : /**
159 : * @brief Disable transfer in ICU on this activation source.
160 : *
161 : * @param activation_irq activation source.
162 : *
163 : * @retval 0 On success.
164 : * @retval -EINVAL if activation source is invalid.
165 : */
166 1 : int dtc_renesas_rx_disable_transfer(uint8_t activation_irq);
167 :
168 : /**
169 : * @brief Start transfers on this activation source.
170 : *
171 : * @param dev DTC device instance.
172 : * @param activation_irq activation source.
173 : *
174 : * @retval 0 On success.
175 : * @retval -EINVAL if activation source is invalid.
176 : * @retval -EACCES if this activation source in dtc vector table is not configured.
177 : */
178 1 : int dtc_renesas_rx_start_transfer(const struct device *dev, uint8_t activation_irq);
179 :
180 : /**
181 : * @brief Stop transfers on this activation source.
182 : *
183 : * @param dev DTC device instance.
184 : * @param activation_irq activation source.
185 : *
186 : * @retval 0 On success.
187 : * @retval -EINVAL if activation source is invalid.
188 : * @retval -EACCES if this activation source in dtc vector table is not configured.
189 : */
190 1 : int dtc_renesas_rx_stop_transfer(const struct device *dev, uint8_t activation_irq);
191 :
192 : /**
193 : * @brief Reset transfer on this activation source.
194 : *
195 : * @param dev DTC device instance.
196 : * @param activation_irq Activation source IRQ number.
197 : * @param p_src Pointer to the source address for the transfer.
198 : * @param p_dest Pointer to the destination address for the transfer.
199 : * @param num_transfers Number of data units to transfer.
200 : *
201 : * @retval 0 On success.
202 : * @retval -EINVAL If activation source is invalid.
203 : */
204 1 : int dtc_renesas_rx_reset_transfer(const struct device *dev, uint8_t activation_irq,
205 : void const *p_src, void *p_dest, uint16_t const num_transfers);
206 :
207 : /**
208 : * @brief Get status transfer of DTC module and store it into status pointer.
209 : *
210 : * @param dev DTC device instance.
211 : * @param status DTC status.
212 : */
213 1 : void dtc_renesas_rx_get_transfer_status(const struct device *dev,
214 : struct dtc_transfer_status *status);
215 :
216 : /**
217 : * @brief Get information about this transfer and store it into p_properties.
218 : *
219 : * @param dev DTC device instance.
220 : * @param activation_irq Activation source IRQ number.
221 : * @param p_properties Pointer to structure to receive driver-specific transfer properties.
222 : *
223 : * @retval 0 On success.
224 : * @retval -EINVAL If activation source is invalid.
225 : */
226 1 : int dtc_renesas_rx_info_get(const struct device *dev, uint8_t activation_irq,
227 : transfer_properties_t *const p_properties);
228 :
229 0 : static ALWAYS_INLINE bool is_valid_activation_irq(uint8_t activation_irq)
230 : {
231 : if (activation_irq < 0 || activation_irq > DTC_VECTOR_TABLE_ENTRIES) {
232 : return false;
233 : }
234 :
235 : return true;
236 : }
237 :
238 : #endif /* ZEPHYR_DRIVERS_MISC_RENESAS_RX_DTC_H_ */
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