Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2025 Tenstorrent AI ULC
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DRIVERS_MSPI_DW_H_
       8              : #define ZEPHYR_INCLUDE_DRIVERS_MSPI_DW_H_
       9              : 
      10              : #ifdef __cplusplus
      11              : extern "C" {
      12              : #endif
      13              : 
      14              : /**
      15              :  * Designware MSPI configuration structure- this should be passed to the
      16              :  * MSPI driver when calling mspi_timing_config
      17              :  */
      18            1 : struct mspi_dw_timing_cfg {
      19            0 :         uint32_t rx_sample_dly; /* RX sample delay, written to RX_SAMPLE_DLY register */
      20              : };
      21              : 
      22              : /* Configure RX_SAMPLE_DLY register for MSPI DW SSI */
      23            0 : #define MSPI_DW_RX_TIMING_CFG BIT(0)
      24              : 
      25              : #ifdef __cplusplus
      26              : }
      27              : #endif
      28              : 
      29              : #endif /* ZEPHYR_INCLUDE_DRIVERS_MSPI_DW_H_ */