Line data    Source code

       1           1 : /*
       2             :  * Copyright (c) 2022-2023, Intel Corporation.
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef ZEPHYR_INCLUDE_SIP_SVC_AGILEX_SMC_H_
       8             : #define ZEPHYR_INCLUDE_SIP_SVC_AGILEX_SMC_H_
       9             : 
      10             : /**
      11             :  * @file
      12             :  * @brief Intel SoC FPGA Agilex customized Arm SiP Services
      13             :  *        SMC protocol.
      14             :  */
      15             : 
      16             : /* @brief SMC return status
      17             :  */
      18             : 
      19           0 : #define SMC_STATUS_INVALID     0xFFFFFFFF
      20           0 : #define SMC_STATUS_OKAY        0
      21           0 : #define SMC_STATUS_BUSY        1
      22           0 : #define SMC_STATUS_REJECT      2
      23           0 : #define SMC_STATUS_NO_RESPONSE 3
      24           0 : #define SMC_STATUS_ERROR       4
      25             : 
      26             : /* @brief SMC Intel Header at a1
      27             :  *
      28             :  * bit
      29             :  *  7: 0   Transaction ID
      30             :  * 59: 8   Reserved
      31             :  * 63:60   Version
      32             :  */
      33           0 : #define SMC_PLAT_PROTO_VER 0x0
      34             : 
      35           0 : #define SMC_PLAT_PROTO_HEADER_TRANS_ID_OFFSET 0
      36           0 : #define SMC_PLAT_PROTO_HEADER_TRANS_ID_MASK   0xFF
      37             : 
      38           0 : #define SMC_PLAT_PROTO_HEADER_VER_OFFSET 60
      39           0 : #define SMC_PLAT_PROTO_HEADER_VER_MASK   0xF
      40             : 
      41           0 : #define SMC_PLAT_PROTO_HEADER                                                                      \
      42             :         ((SMC_PLAT_PROTO_VER & SMC_PLAT_PROTO_HEADER_VER_MASK) << SMC_PLAT_PROTO_HEADER_VER_OFFSET)
      43             : 
      44           0 : #define SMC_PLAT_PROTO_HEADER_SET_TRANS_ID(header, trans_id)                                       \
      45             :         (header) &=                                                                                \
      46             :                 ~(SMC_PLAT_PROTO_HEADER_TRANS_ID_MASK << SMC_PLAT_PROTO_HEADER_TRANS_ID_OFFSET);   \
      47             :         (header) |= (((trans_id)&SMC_PLAT_PROTO_HEADER_TRANS_ID_MASK)                              \
      48             :                      << SMC_PLAT_PROTO_HEADER_TRANS_ID_OFFSET);
      49             : 
      50             : /* @brief SYNC SMC Function IDs
      51             :  */
      52             : 
      53           0 : #define SMC_FUNC_ID_GET_SVC_VERSION 0xC2000400
      54           0 : #define SMC_FUNC_ID_REG_READ        0xC2000401
      55           0 : #define SMC_FUNC_ID_REG_WRITE       0xC2000402
      56           0 : #define SMC_FUNC_ID_REG_UPDATE      0xC2000403
      57           0 : #define SMC_FUNC_ID_SET_HPS_BRIDGES 0xC2000404
      58           0 : #define SMC_FUNC_ID_RSU_UPDATE_ADDR 0xC2000405
      59             : 
      60             : /* @brief ASYNC SMC Function IDs
      61             :  */
      62             : 
      63           0 : #define SMC_FUNC_ID_MAILBOX_SEND_COMMAND  0xC2000420
      64           0 : #define SMC_FUNC_ID_MAILBOX_POLL_RESPONSE 0xC2000421
      65             : 
      66             : /* @brief SDM mailbox CANCEL command
      67             :  */
      68           0 : #define MAILBOX_CANCEL_COMMAND 0x03
      69             : 
      70             : #endif /* ZEPHYR_INCLUDE_SIP_SVC_AGILEX_SMC_H_ */