Line data    Source code

       1            0 : /*
       2              :  * Copyright 2022 BrainCo Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_GD32F3X0_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_GD32F3X0_H_
       8              : 
       9              : /*
      10              :  * ADC clock and prescaler definition refer from rcu_adc_clock_enum which
      11              :  * defined at GD32F3X0 RCU HAL.
      12              :  */
      13            0 : #define GD32_RCU_ADCCK_IRC28M_DIV2      0
      14            0 : #define GD32_RCU_ADCCK_IRC28M           1
      15            0 : #define GD32_RCU_ADCCK_APB2_DIV2        2
      16            0 : #define GD32_RCU_ADCCK_AHB_DIV3         3
      17            0 : #define GD32_RCU_ADCCK_APB2_DIV4        4
      18            0 : #define GD32_RCU_ADCCK_AHB_DIV5         5
      19            0 : #define GD32_RCU_ADCCK_APB2_DIV6        6
      20            0 : #define GD32_RCU_ADCCK_AHB_DIV7         7
      21            0 : #define GD32_RCU_ADCCK_APB2_DIV8        8
      22            0 : #define GD32_RCU_ADCCK_AHB_DIV9         9
      23              : 
      24              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_GD32F3X0_H_ */