Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL61X_CLOCK_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL61X_CLOCK_H_
       9              : 
      10              : #include "bflb_clock_common.h"
      11              : 
      12            0 : #define BL61X_CLKID_CLK_ROOT    BFLB_CLKID_CLK_ROOT
      13            0 : #define BL61X_CLKID_CLK_RC32M   BFLB_CLKID_CLK_RC32M
      14            0 : #define BL61X_CLKID_CLK_CRYSTAL BFLB_CLKID_CLK_CRYSTAL
      15            0 : #define BL61X_CLKID_CLK_BCLK    BFLB_CLKID_CLK_BCLK
      16            0 : #define BL61X_CLKID_CLK_WIFIPLL 4
      17            0 : #define BL61X_CLKID_CLK_AUPLL   5
      18              : 
      19            0 : #define BL61X_AUPLL_DIV2        0
      20            0 : #define BL61X_AUPLL_DIV1        1
      21            0 : #define BL61X_WIFIPLL_240MHz    2
      22            0 : #define BL61X_WIFIPLL_320MHz    3
      23              : 
      24              : /* Overclocked
      25              :  * Overclock PLL to 480MHz for div ID 1 and 360MHz for div ID 2
      26              :  * BCLK divider MUST be set so BCLK is 80MHz or slower
      27              :  * Breaks most complex peripherals (Wifi)
      28              :  */
      29            0 : #define BL61X_WIFIPLL_OC_360MHz (2 | 0x10)
      30            0 : #define BL61X_WIFIPLL_OC_480MHz (3 | 0x10)
      31              : 
      32              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL61X_CLOCK_H_ */