Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2024 Michael Hope
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_CH32V00X_CLOCKS_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_CH32V00X_CLOCKS_H_
       9              : 
      10            0 : #define CH32V00X_HB_PCENR_OFFSET  0
      11            0 : #define CH32V00X_PB2_PCENR_OFFSET 1
      12            0 : #define CH32V00X_PB1_PCENR_OFFSET 2
      13              : 
      14            0 : #define CH32V00X_CLOCK_CONFIG(bus, bit) (((CH32V00X_##bus##_PCENR_OFFSET) << 5) | (bit))
      15              : 
      16            0 : #define CH32V00X_CLOCK_DMA1 CH32V00X_CLOCK_CONFIG(HB, 0)
      17            0 : #define CH32V00X_CLOCK_SRAM CH32V00X_CLOCK_CONFIG(HB, 2)
      18              : 
      19            0 : #define CH32V00X_CLOCK_AFIO   CH32V00X_CLOCK_CONFIG(PB2, 0)
      20            0 : #define CH32V00X_CLOCK_IOPA   CH32V00X_CLOCK_CONFIG(PB2, 2)
      21            0 : #define CH32V00X_CLOCK_IOPB   CH32V00X_CLOCK_CONFIG(PB2, 3)
      22            0 : #define CH32V00X_CLOCK_IOPC   CH32V00X_CLOCK_CONFIG(PB2, 4)
      23            0 : #define CH32V00X_CLOCK_IOPD   CH32V00X_CLOCK_CONFIG(PB2, 5)
      24            0 : #define CH32V00X_CLOCK_ADC1   CH32V00X_CLOCK_CONFIG(PB2, 9)
      25            0 : #define CH32V00X_CLOCK_TIM1   CH32V00X_CLOCK_CONFIG(PB2, 11)
      26            0 : #define CH32V00X_CLOCK_SPI1   CH32V00X_CLOCK_CONFIG(PB2, 12)
      27            0 : #define CH32V00X_CLOCK_USART2 CH32V00X_CLOCK_CONFIG(PB2, 13)
      28            0 : #define CH32V00X_CLOCK_USART1 CH32V00X_CLOCK_CONFIG(PB2, 14)
      29              : 
      30            0 : #define CH32V00X_CLOCK_TIM2 CH32V00X_CLOCK_CONFIG(PB1, 0)
      31            0 : #define CH32V00X_CLOCK_TIM3 CH32V00X_CLOCK_CONFIG(PB1, 2)
      32            0 : #define CH32V00X_CLOCK_WWDG CH32V00X_CLOCK_CONFIG(PB1, 11)
      33            0 : #define CH32V00X_CLOCK_I2C1 CH32V00X_CLOCK_CONFIG(PB1, 21)
      34            0 : #define CH32V00X_CLOCK_PWR  CH32V00X_CLOCK_CONFIG(PB1, 28)
      35              : 
      36              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_CH32V00X_CLOCKS_H_ */