Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef __CH32V20X_V30X_CLOCKS_H__
       8              : #define __CH32V20X_V30X_CLOCKS_H__
       9              : 
      10            0 : #define CH32V20X_V30X_AHB_PCENR_OFFSET  0
      11            0 : #define CH32V20X_V30X_APB2_PCENR_OFFSET 1
      12            0 : #define CH32V20X_V30X_APB1_PCENR_OFFSET 2
      13              : 
      14            0 : #define CH32V20X_V30X_CLOCK_CONFIG(bus, bit) (((CH32V20X_V30X_##bus##_PCENR_OFFSET) << 5) | (bit))
      15              : 
      16            0 : #define CH32V20X_V30X_CLOCK_DMA1     CH32V20X_V30X_CLOCK_CONFIG(AHB, 0)
      17            0 : #define CH32V20X_V30X_CLOCK_DMA2     CH32V20X_V30X_CLOCK_CONFIG(AHB, 1)
      18            0 : #define CH32V20X_V30X_CLOCK_SRAM     CH32V20X_V30X_CLOCK_CONFIG(AHB, 2)
      19            0 : #define CH32V20X_V30X_CLOCK_FLITF    CH32V20X_V30X_CLOCK_CONFIG(AHB, 4)
      20            0 : #define CH32V20X_V30X_CLOCK_CRC      CH32V20X_V30X_CLOCK_CONFIG(AHB, 6)
      21            0 : #define CH32V20X_V30X_CLOCK_FSMC     CH32V20X_V30X_CLOCK_CONFIG(AHB, 8)
      22            0 : #define CH32V20X_V30X_CLOCK_RNG      CH32V20X_V30X_CLOCK_CONFIG(AHB, 9)
      23            0 : #define CH32V20X_V30X_CLOCK_SDIO     CH32V20X_V30X_CLOCK_CONFIG(AHB, 10)
      24            0 : #define CH32V20X_V30X_CLOCK_USBHS    CH32V20X_V30X_CLOCK_CONFIG(AHB, 11)
      25            0 : #define CH32V20X_V30X_CLOCK_OTG_FS   CH32V20X_V30X_CLOCK_CONFIG(AHB, 12)
      26            0 : #define CH32V20X_V30X_CLOCK_DVP      CH32V20X_V30X_CLOCK_CONFIG(AHB, 13)
      27            0 : #define CH32V20X_V30X_CLOCK_ETHMAC   CH32V20X_V30X_CLOCK_CONFIG(AHB, 14)
      28            0 : #define CH32V20X_V30X_CLOCK_ETHMACTX CH32V20X_V30X_CLOCK_CONFIG(AHB, 15)
      29            0 : #define CH32V20X_V30X_CLOCK_ETHMACRX CH32V20X_V30X_CLOCK_CONFIG(AHB, 16)
      30            0 : #define CH32V20X_V30X_CLOCK_BLEC     CH32V20X_V30X_CLOCK_CONFIG(AHB, 16)
      31            0 : #define CH32V20X_V30X_CLOCK_BLES     CH32V20X_V30X_CLOCK_CONFIG(AHB, 17)
      32              : 
      33            0 : #define CH32V20X_V30X_CLOCK_AFIO   CH32V20X_V30X_CLOCK_CONFIG(APB2, 0)
      34            0 : #define CH32V20X_V30X_CLOCK_IOPA   CH32V20X_V30X_CLOCK_CONFIG(APB2, 2)
      35            0 : #define CH32V20X_V30X_CLOCK_IOPB   CH32V20X_V30X_CLOCK_CONFIG(APB2, 3)
      36            0 : #define CH32V20X_V30X_CLOCK_IOPC   CH32V20X_V30X_CLOCK_CONFIG(APB2, 4)
      37            0 : #define CH32V20X_V30X_CLOCK_IOPD   CH32V20X_V30X_CLOCK_CONFIG(APB2, 5)
      38            0 : #define CH32V20X_V30X_CLOCK_IOPE   CH32V20X_V30X_CLOCK_CONFIG(APB2, 6)
      39            0 : #define CH32V20X_V30X_CLOCK_ADC1   CH32V20X_V30X_CLOCK_CONFIG(APB2, 9)
      40            0 : #define CH32V20X_V30X_CLOCK_ADC2   CH32V20X_V30X_CLOCK_CONFIG(APB2, 10)
      41            0 : #define CH32V20X_V30X_CLOCK_TIM1   CH32V20X_V30X_CLOCK_CONFIG(APB2, 11)
      42            0 : #define CH32V20X_V30X_CLOCK_SPI1   CH32V20X_V30X_CLOCK_CONFIG(APB2, 12)
      43            0 : #define CH32V20X_V30X_CLOCK_TIM8   CH32V20X_V30X_CLOCK_CONFIG(APB2, 13)
      44            0 : #define CH32V20X_V30X_CLOCK_USART1 CH32V20X_V30X_CLOCK_CONFIG(APB2, 14)
      45            0 : #define CH32V20X_V30X_CLOCK_TIM9   CH32V20X_V30X_CLOCK_CONFIG(APB2, 19)
      46            0 : #define CH32V20X_V30X_CLOCK_TIM10  CH32V20X_V30X_CLOCK_CONFIG(APB2, 20)
      47              : 
      48            0 : #define CH32V20X_V30X_CLOCK_TIM2   CH32V20X_V30X_CLOCK_CONFIG(APB1, 0)
      49            0 : #define CH32V20X_V30X_CLOCK_TIM3   CH32V20X_V30X_CLOCK_CONFIG(APB1, 1)
      50            0 : #define CH32V20X_V30X_CLOCK_TIM4   CH32V20X_V30X_CLOCK_CONFIG(APB1, 2)
      51            0 : #define CH32V20X_V30X_CLOCK_TIM5   CH32V20X_V30X_CLOCK_CONFIG(APB1, 3)
      52            0 : #define CH32V20X_V30X_CLOCK_TIM6   CH32V20X_V30X_CLOCK_CONFIG(APB1, 4)
      53            0 : #define CH32V20X_V30X_CLOCK_TIM7   CH32V20X_V30X_CLOCK_CONFIG(APB1, 5)
      54            0 : #define CH32V20X_V30X_CLOCK_USART6 CH32V20X_V30X_CLOCK_CONFIG(APB1, 6)
      55            0 : #define CH32V20X_V30X_CLOCK_USART7 CH32V20X_V30X_CLOCK_CONFIG(APB1, 7)
      56            0 : #define CH32V20X_V30X_CLOCK_USART8 CH32V20X_V30X_CLOCK_CONFIG(APB1, 8)
      57            0 : #define CH32V20X_V30X_CLOCK_WWDG   CH32V20X_V30X_CLOCK_CONFIG(APB1, 11)
      58            0 : #define CH32V20X_V30X_CLOCK_SPI2   CH32V20X_V30X_CLOCK_CONFIG(APB1, 14)
      59            0 : #define CH32V20X_V30X_CLOCK_SPI3   CH32V20X_V30X_CLOCK_CONFIG(APB1, 15)
      60            0 : #define CH32V20X_V30X_CLOCK_USART2 CH32V20X_V30X_CLOCK_CONFIG(APB1, 17)
      61            0 : #define CH32V20X_V30X_CLOCK_USART3 CH32V20X_V30X_CLOCK_CONFIG(APB1, 18)
      62            0 : #define CH32V20X_V30X_CLOCK_USART4 CH32V20X_V30X_CLOCK_CONFIG(APB1, 19)
      63            0 : #define CH32V20X_V30X_CLOCK_USART5 CH32V20X_V30X_CLOCK_CONFIG(APB1, 20)
      64            0 : #define CH32V20X_V30X_CLOCK_I2C1   CH32V20X_V30X_CLOCK_CONFIG(APB1, 21)
      65            0 : #define CH32V20X_V30X_CLOCK_I2C2   CH32V20X_V30X_CLOCK_CONFIG(APB1, 22)
      66            0 : #define CH32V20X_V30X_CLOCK_USBD   CH32V20X_V30X_CLOCK_CONFIG(APB1, 23)
      67            0 : #define CH32V20X_V30X_CLOCK_CAN1   CH32V20X_V30X_CLOCK_CONFIG(APB1, 25)
      68            0 : #define CH32V20X_V30X_CLOCK_CAN2   CH32V20X_V30X_CLOCK_CONFIG(APB1, 26)
      69            0 : #define CH32V20X_V30X_CLOCK_BKP    CH32V20X_V30X_CLOCK_CONFIG(APB1, 27)
      70            0 : #define CH32V20X_V30X_CLOCK_PWR    CH32V20X_V30X_CLOCK_CONFIG(APB1, 28)
      71            0 : #define CH32V20X_V30X_CLOCK_DAC    CH32V20X_V30X_CLOCK_CONFIG(APB1, 29)
      72              : 
      73              : #endif