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1 0 : /* 2 : * Copyright (c) 2020 Mohamed ElShahawi 3 : * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. 4 : * 5 : * SPDX-License-Identifier: Apache-2.0 6 : */ 7 : 8 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ 9 : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ 10 : 11 : /* Supported CPU clock Sources */ 12 0 : #define ESP32_CPU_CLK_SRC_XTAL 0U 13 0 : #define ESP32_CPU_CLK_SRC_PLL 1U 14 0 : #define ESP32_CLK_SRC_RC_FAST 2U 15 0 : #define ESP32_CLK_SRC_APLL_CLK 3U 16 : 17 : /* Supported PLL CPU frequencies */ 18 0 : #define ESP32_CLK_CPU_PLL_80M 80000000 19 0 : #define ESP32_CLK_CPU_PLL_160M 160000000 20 0 : #define ESP32_CLK_CPU_PLL_240M 240000000 21 0 : #define ESP32_CLK_CPU_RC_FAST_FREQ 1062500 22 : 23 : /* Supported XTAL frequencies */ 24 0 : #define ESP32_CLK_XTAL_24M 24000000 25 0 : #define ESP32_CLK_XTAL_26M 26000000 26 0 : #define ESP32_CLK_XTAL_40M 40000000 27 : 28 : /* Supported RTC fast clock sources */ 29 0 : #define ESP32_RTC_FAST_CLK_SRC_XTAL_D4 0 30 0 : #define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 31 : 32 : /* Supported RTC slow clock sources */ 33 0 : #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 34 0 : #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 35 0 : #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 36 0 : #define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 37 : 38 : /* RTC slow clock frequencies */ 39 0 : #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 150000 40 0 : #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 41 0 : #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 33203 42 : 43 : /* Modules IDs 44 : * These IDs are actually offsets in CLK and RST Control registers. 45 : * These IDs shouldn't be changed unless there is a Hardware change 46 : * from Espressif. 47 : * 48 : * Basic Modules 49 : * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG 50 : */ 51 0 : #define ESP32_LEDC_MODULE 0 52 0 : #define ESP32_UART0_MODULE 1 53 0 : #define ESP32_UART1_MODULE 2 54 0 : #define ESP32_UART2_MODULE 3 55 0 : #define ESP32_I2C0_MODULE 4 56 0 : #define ESP32_I2C1_MODULE 5 57 0 : #define ESP32_I2S0_MODULE 6 58 0 : #define ESP32_I2S1_MODULE 7 59 0 : #define ESP32_TIMG0_MODULE 8 60 0 : #define ESP32_TIMG1_MODULE 9 61 0 : #define ESP32_PWM0_MODULE 10 62 0 : #define ESP32_PWM1_MODULE 11 63 0 : #define ESP32_UHCI0_MODULE 12 64 0 : #define ESP32_UHCI1_MODULE 13 65 0 : #define ESP32_RMT_MODULE 14 66 0 : #define ESP32_PCNT_MODULE 15 67 0 : #define ESP32_SPI_MODULE 16 68 0 : #define ESP32_HSPI_MODULE 17 69 0 : #define ESP32_VSPI_MODULE 18 70 0 : #define ESP32_SPI_DMA_MODULE 19 71 0 : #define ESP32_SDMMC_MODULE 20 72 0 : #define ESP32_SDIO_SLAVE_MODULE 21 73 0 : #define ESP32_TWAI_MODULE 22 74 0 : #define ESP32_CAN_MODULE ESP32_TWAI_MODULE 75 0 : #define ESP32_EMAC_MODULE 23 76 0 : #define ESP32_RNG_MODULE 24 77 0 : #define ESP32_WIFI_MODULE 25 78 0 : #define ESP32_BT_MODULE 26 79 0 : #define ESP32_WIFI_BT_COMMON_MODULE 27 80 0 : #define ESP32_BT_BASEBAND_MODULE 28 81 0 : #define ESP32_BT_LC_MODULE 29 82 0 : #define ESP32_AES_MODULE 30 83 0 : #define ESP32_SHA_MODULE 31 84 0 : #define ESP32_RSA_MODULE 32 85 0 : #define ESP32_SARADC_MODULE 33 86 0 : #define ESP32_MODULE_MAX 34 87 : 88 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ */