Line data Source code
1 0 : /* 2 : * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. 3 : * 4 : * SPDX-License-Identifier: Apache-2.0 5 : */ 6 : 7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ 8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ 9 : 10 : /* Supported CPU clock Sources */ 11 0 : #define ESP32_CPU_CLK_SRC_XTAL 0U 12 0 : #define ESP32_CPU_CLK_SRC_PLL 1U 13 0 : #define ESP32_CLK_SRC_RC_FAST 2U 14 : 15 : /* Supported CPU frequencies */ 16 0 : #define ESP32_CLK_CPU_PLL_40M 40000000 17 0 : #define ESP32_CLK_CPU_PLL_60M 60000000 18 0 : #define ESP32_CLK_CPU_PLL_80M 80000000 19 0 : #define ESP32_CLK_CPU_PLL_120M 120000000 20 0 : #define ESP32_CLK_CPU_RC_FAST_FREQ 8750000 21 : 22 : /* Supported XTAL frequencies */ 23 0 : #define ESP32_CLK_XTAL_26M 26000000 24 0 : #define ESP32_CLK_XTAL_32M 32000000 25 0 : #define ESP32_CLK_XTAL_40M 40000000 26 : 27 : /* Supported RTC fast clock sources */ 28 0 : #define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 0 29 0 : #define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 30 : 31 : /* Supported RTC slow clock sources */ 32 0 : #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 33 0 : #define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW 1 34 0 : #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 35 : 36 : /* RTC slow clock frequencies */ 37 0 : #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000 38 0 : #define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW_FREQ 32768 39 0 : #define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 68359 40 : 41 : /* Modules IDs 42 : * These IDs are actually offsets in CLK and RST Control registers. 43 : * These IDs shouldn't be changed unless there is a Hardware change 44 : * from Espressif. 45 : * 46 : * Basic Modules 47 : * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG 48 : */ 49 0 : #define ESP32_LEDC_MODULE 0 50 0 : #define ESP32_UART0_MODULE 1 51 0 : #define ESP32_UART1_MODULE 2 52 0 : #define ESP32_I2C0_MODULE 3 53 0 : #define ESP32_TIMG0_MODULE 4 54 0 : #define ESP32_TIMG1_MODULE 5 /* No timg1 on esp32c2, TODO: IDF-3825 */ 55 0 : #define ESP32_UHCI0_MODULE 6 56 0 : #define ESP32_SPI_MODULE 7 /* SPI1 */ 57 0 : #define ESP32_SPI2_MODULE 8 /* SPI2 */ 58 0 : #define ESP32_RNG_MODULE 9 59 0 : #define ESP32_WIFI_MODULE 10 60 0 : #define ESP32_BT_MODULE 11 61 0 : #define ESP32_WIFI_BT_COMMON_MODULE 12 62 0 : #define ESP32_BT_BASEBAND_MODULE 13 63 0 : #define ESP32_BT_LC_MODULE 14 64 0 : #define ESP32_AES_MODULE 15 65 0 : #define ESP32_SHA_MODULE 16 66 0 : #define ESP32_ECC_MODULE 17 67 0 : #define ESP32_GDMA_MODULE 18 68 0 : #define ESP32_SYSTIMER_MODULE 19 69 0 : #define ESP32_SARADC_MODULE 20 70 0 : #define ESP32_TEMPSENSOR_MODULE 21 71 0 : #define ESP32_MODEM_RPA_MODULE 22 72 0 : #define ESP32_MODULE_MAX 23 73 : 74 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ */