Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_
       9              : 
      10              : /* Supported CPU clock Sources */
      11            0 : #define ESP32_CPU_CLK_SRC_XTAL 0U
      12            0 : #define ESP32_CPU_CLK_SRC_PLL  1U
      13            0 : #define ESP32_CLK_SRC_RC_FAST  2U
      14              : 
      15              : /* Supported CPU frequencies */
      16            0 : #define ESP32_CLK_CPU_PLL_80M      80000000
      17            0 : #define ESP32_CLK_CPU_PLL_160M     160000000
      18            0 : #define ESP32_CLK_CPU_RC_FAST_FREQ 17500000
      19              : 
      20              : /* Supported XTAL Frequencies */
      21            0 : #define ESP32_CLK_XTAL_32M 32000000
      22            0 : #define ESP32_CLK_XTAL_40M 40000000
      23              : 
      24              : /* Supported RTC fast clock sources */
      25            0 : #define ESP32_RTC_FAST_CLK_SRC_RC_FAST 0
      26            0 : #define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 1
      27              : 
      28              : /* Supported RTC slow clock frequencies */
      29            0 : #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0
      30            0 : #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1
      31            0 : #define ESP32_RTC_SLOW_CLK_SRC_RC32K   2
      32            0 : #define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9
      33              : 
      34              : /* RTC slow clock frequencies */
      35            0 : #define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000
      36            0 : #define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768
      37            0 : #define ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ   32768
      38              : 
      39              : /* Modules IDs
      40              :  * These IDs are actually offsets in CLK and RST Control registers.
      41              :  * These IDs shouldn't be changed unless there is a Hardware change
      42              :  * from Espressif.
      43              :  *
      44              :  * Basic Modules
      45              :  * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
      46              :  */
      47            0 : #define ESP32_LEDC_MODULE                0
      48            0 : #define ESP32_UART0_MODULE               1
      49            0 : #define ESP32_UART1_MODULE               2
      50            0 : #define ESP32_USB_MODULE                 3
      51            0 : #define ESP32_I2C0_MODULE                4
      52            0 : #define ESP32_I2S1_MODULE                5
      53            0 : #define ESP32_TIMG0_MODULE               6
      54            0 : #define ESP32_TIMG1_MODULE               7
      55            0 : #define ESP32_UHCI0_MODULE               8
      56            0 : #define ESP32_RMT_MODULE                 9
      57            0 : #define ESP32_PCNT_MODULE                10
      58            0 : #define ESP32_SPI_MODULE                 11
      59            0 : #define ESP32_SPI2_MODULE                12
      60            0 : #define ESP32_TWAI0_MODULE               13
      61            0 : #define ESP32_TWAI1_MODULE               14
      62            0 : #define ESP32_RNG_MODULE                 15
      63            0 : #define ESP32_RSA_MODULE                 16
      64            0 : #define ESP32_AES_MODULE                 17
      65            0 : #define ESP32_SHA_MODULE                 18
      66            0 : #define ESP32_ECC_MODULE                 19
      67            0 : #define ESP32_HMAC_MODULE                20
      68            0 : #define ESP32_DS_MODULE                  21
      69            0 : #define ESP32_SDIO_SLAVE_MODULE          22
      70            0 : #define ESP32_GDMA_MODULE                23
      71            0 : #define ESP32_MCPWM0_MODULE              24
      72            0 : #define ESP32_ETM_MODULE                 25
      73            0 : #define ESP32_PARLIO_MODULE              26
      74            0 : #define ESP32_SYSTIMER_MODULE            27
      75            0 : #define ESP32_SARADC_MODULE              28
      76            0 : #define ESP32_TEMPSENSOR_MODULE          29
      77            0 : #define ESP32_ASSIST_DEBUG_MODULE        30
      78              : /* LP peripherals */
      79            0 : #define ESP32_LP_I2C0_MODULE             31
      80            0 : #define ESP32_LP_UART0_MODULE            32
      81              : /* Peripherals clock managed by the modem_clock driver must be listed last */
      82            0 : #define ESP32_WIFI_MODULE                33
      83            0 : #define ESP32_BT_MODULE                  34
      84            0 : #define ESP32_IEEE802154_MODULE          35
      85            0 : #define ESP32_COEX_MODULE                36
      86            0 : #define ESP32_PHY_MODULE                 37
      87            0 : #define ESP32_ANA_I2C_MASTER_MODULE      38
      88            0 : #define ESP32_MODEM_ETM_MODULE           39
      89            0 : #define ESP32_MODEM_ADC_COMMON_FE_MODULE 40
      90            0 : #define ESP32_MODULE_MAX                 41
      91              : 
      92              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_ */