Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_
       9              : 
      10              : #include "gd32-clocks-common.h"
      11              : 
      12              : /**
      13              :  * @name Register offsets
      14              :  * @{
      15              :  */
      16              : 
      17            0 : #define GD32_AHBEN_OFFSET        0x14U
      18            0 : #define GD32_APB1EN_OFFSET       0x1CU
      19            0 : #define GD32_APB2EN_OFFSET       0x18U
      20              : 
      21              : /** @} */
      22              : 
      23              : /**
      24              :  * @name Clock enable/disable definitions for peripherals
      25              :  * @{
      26              :  */
      27              : 
      28              : /* AHB peripherals */
      29            0 : #define GD32_CLOCK_DMA0     GD32_CLOCK_CONFIG(AHBEN, 0U)
      30            0 : #define GD32_CLOCK_DMA1     GD32_CLOCK_CONFIG(AHBEN, 1U)
      31            0 : #define GD32_CLOCK_SRAMSP   GD32_CLOCK_CONFIG(AHBEN, 2U)
      32            0 : #define GD32_CLOCK_DMAMUX   GD32_CLOCK_CONFIG(AHBEN, 3U)
      33            0 : #define GD32_CLOCK_FMCSP    GD32_CLOCK_CONFIG(AHBEN, 4U)
      34            0 : #define GD32_CLOCK_CRC      GD32_CLOCK_CONFIG(AHBEN, 6U)
      35            0 : #define GD32_CLOCK_MFCOM    GD32_CLOCK_CONFIG(AHBEN, 14U)
      36            0 : #define GD32_CLOCK_GPIOA    GD32_CLOCK_CONFIG(AHBEN, 17U)
      37            0 : #define GD32_CLOCK_GPIOB    GD32_CLOCK_CONFIG(AHBEN, 18U)
      38            0 : #define GD32_CLOCK_GPIOC    GD32_CLOCK_CONFIG(AHBEN, 19U)
      39            0 : #define GD32_CLOCK_GPIOD    GD32_CLOCK_CONFIG(AHBEN, 20U)
      40            0 : #define GD32_CLOCK_GPIOE    GD32_CLOCK_CONFIG(AHBEN, 21U)
      41            0 : #define GD32_CLOCK_GPIOF    GD32_CLOCK_CONFIG(AHBEN, 22U)
      42              : 
      43              : /* APB1 peripherals */
      44            0 : #define GD32_CLOCK_TIMER1     GD32_CLOCK_CONFIG(APB1EN, 0U)
      45            0 : #define GD32_CLOCK_TIMER5     GD32_CLOCK_CONFIG(APB1EN, 4U)
      46            0 : #define GD32_CLOCK_TIMER6     GD32_CLOCK_CONFIG(APB1EN, 5U)
      47            0 : #define GD32_CLOCK_WWDGT      GD32_CLOCK_CONFIG(APB1EN, 11U)
      48            0 : #define GD32_CLOCK_SPI1       GD32_CLOCK_CONFIG(APB1EN, 14U)
      49            0 : #define GD32_CLOCK_USART1     GD32_CLOCK_CONFIG(APB1EN, 17U)
      50            0 : #define GD32_CLOCK_USART2     GD32_CLOCK_CONFIG(APB1EN, 18U)
      51            0 : #define GD32_CLOCK_I2C0       GD32_CLOCK_CONFIG(APB1EN, 21U)
      52            0 : #define GD32_CLOCK_I2C1       GD32_CLOCK_CONFIG(APB1EN, 22U)
      53            0 : #define GD32_CLOCK_BKP        GD32_CLOCK_CONFIG(APB1EN, 26U)
      54            0 : #define GD32_CLOCK_PMU        GD32_CLOCK_CONFIG(APB1EN, 28U)
      55            0 : #define GD32_CLOCK_DAC        GD32_CLOCK_CONFIG(APB1EN, 29U)
      56              : 
      57              : /* APB2 peripherals */
      58            0 : #define GD32_CLOCK_SYSCFG     GD32_CLOCK_CONFIG(APB2EN, 0U)
      59            0 : #define GD32_CLOCK_CMP        GD32_CLOCK_CONFIG(APB2EN, 1U)
      60            0 : #define GD32_CLOCK_ADC0       GD32_CLOCK_CONFIG(APB2EN, 9U)
      61            0 : #define GD32_CLOCK_ADC1       GD32_CLOCK_CONFIG(APB2EN, 10U)
      62            0 : #define GD32_CLOCK_TIMER0     GD32_CLOCK_CONFIG(APB2EN, 11U)
      63            0 : #define GD32_CLOCK_SPI0       GD32_CLOCK_CONFIG(APB2EN, 12U)
      64            0 : #define GD32_CLOCK_TIMER7     GD32_CLOCK_CONFIG(APB2EN, 13U)
      65            0 : #define GD32_CLOCK_USART0     GD32_CLOCK_CONFIG(APB2EN, 14U)
      66            0 : #define GD32_CLOCK_TIMER19    GD32_CLOCK_CONFIG(APB2EN, 20U)
      67            0 : #define GD32_CLOCK_TIMER20    GD32_CLOCK_CONFIG(APB2EN, 21U)
      68            0 : #define GD32_CLOCK_TRIGSEL    GD32_CLOCK_CONFIG(APB2EN, 29U)
      69            0 : #define GD32_CLOCK_CAN0       GD32_CLOCK_CONFIG(APB2EN, 30U)
      70            0 : #define GD32_CLOCK_CAN1       GD32_CLOCK_CONFIG(APB2EN, 31U)
      71              : 
      72              : /** @} */
      73              : 
      74              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_ */