Line data Source code
1 0 : /*
2 : * Copyright (c) 2022 Teslabs Engineering S.L.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_
9 :
10 : #include "gd32-clocks-common.h"
11 :
12 : /**
13 : * @name Register offsets
14 : * @{
15 : */
16 :
17 0 : #define GD32_AHB1EN_OFFSET 0x30U
18 0 : #define GD32_AHB2EN_OFFSET 0x34U
19 0 : #define GD32_AHB3EN_OFFSET 0x38U
20 0 : #define GD32_APB1EN_OFFSET 0x40U
21 0 : #define GD32_APB2EN_OFFSET 0x44U
22 0 : #define GD32_ADDAPB1EN_OFFSET 0xE4U
23 :
24 : /** @} */
25 :
26 : /**
27 : * @name Clock enable/disable definitions for peripherals
28 : * @{
29 : */
30 :
31 : /* AHB1 peripherals */
32 0 : #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB1EN, 0U)
33 0 : #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB1EN, 1U)
34 0 : #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB1EN, 2U)
35 0 : #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHB1EN, 3U)
36 0 : #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(AHB1EN, 4U)
37 0 : #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHB1EN, 5U)
38 0 : #define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(AHB1EN, 6U)
39 0 : #define GD32_CLOCK_GPIOH GD32_CLOCK_CONFIG(AHB1EN, 7U)
40 0 : #define GD32_CLOCK_GPIOI GD32_CLOCK_CONFIG(AHB1EN, 8U)
41 0 : #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHB1EN, 12U)
42 0 : #define GD32_CLOCK_BKPSRAM GD32_CLOCK_CONFIG(AHB1EN, 18U)
43 0 : #define GD32_CLOCK_TCMSRAM GD32_CLOCK_CONFIG(AHB1EN, 20U)
44 0 : #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHB1EN, 21U)
45 0 : #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHB1EN, 22U)
46 0 : #define GD32_CLOCK_IPA GD32_CLOCK_CONFIG(AHB1EN, 23U)
47 0 : #define GD32_CLOCK_ENET GD32_CLOCK_CONFIG(AHB1EN, 25U)
48 0 : #define GD32_CLOCK_ENETTX GD32_CLOCK_CONFIG(AHB1EN, 26U)
49 0 : #define GD32_CLOCK_ENETRX GD32_CLOCK_CONFIG(AHB1EN, 27U)
50 0 : #define GD32_CLOCK_ENETPTP GD32_CLOCK_CONFIG(AHB1EN, 28U)
51 0 : #define GD32_CLOCK_USBHS GD32_CLOCK_CONFIG(AHB1EN, 29U)
52 0 : #define GD32_CLOCK_USBHSULPI GD32_CLOCK_CONFIG(AHB1EN, 30U)
53 :
54 : /* AHB2 peripherals */
55 0 : #define GD32_CLOCK_DCI GD32_CLOCK_CONFIG(AHB2EN, 0U)
56 0 : #define GD32_CLOCK_TRNG GD32_CLOCK_CONFIG(AHB2EN, 6U)
57 0 : #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHB2EN, 7U)
58 :
59 : /* AHB3 peripherals */
60 0 : #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHB3EN, 0U)
61 :
62 : /* APB1 peripherals */
63 0 : #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
64 0 : #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
65 0 : #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
66 0 : #define GD32_CLOCK_TIMER4 GD32_CLOCK_CONFIG(APB1EN, 3U)
67 0 : #define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U)
68 0 : #define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U)
69 0 : #define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 6U)
70 0 : #define GD32_CLOCK_TIMER12 GD32_CLOCK_CONFIG(APB1EN, 7U)
71 0 : #define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U)
72 0 : #define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U)
73 0 : #define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U)
74 0 : #define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U)
75 0 : #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U)
76 0 : #define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U)
77 0 : #define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U)
78 0 : #define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U)
79 0 : #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U)
80 0 : #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U)
81 0 : #define GD32_CLOCK_I2C2 GD32_CLOCK_CONFIG(APB1EN, 23U)
82 0 : #define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB1EN, 25U)
83 0 : #define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB1EN, 26U)
84 0 : #define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U)
85 0 : #define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U)
86 0 : #define GD32_CLOCK_UART6 GD32_CLOCK_CONFIG(APB1EN, 30U)
87 0 : #define GD32_CLOCK_UART7 GD32_CLOCK_CONFIG(APB1EN, 31U)
88 0 : #define GD32_CLOCK_RTC GD32_CLOCK_CONFIG(BDCTL, 15U)
89 :
90 : /* APB2 peripherals */
91 0 : #define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 0U)
92 0 : #define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 1U)
93 0 : #define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 4U)
94 0 : #define GD32_CLOCK_USART5 GD32_CLOCK_CONFIG(APB2EN, 5U)
95 0 : #define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 8U)
96 0 : #define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 9U)
97 0 : #define GD32_CLOCK_ADC2 GD32_CLOCK_CONFIG(APB2EN, 10U)
98 0 : #define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(APB2EN, 11U)
99 0 : #define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U)
100 0 : #define GD32_CLOCK_SPI3 GD32_CLOCK_CONFIG(APB2EN, 13U)
101 0 : #define GD32_CLOCK_SYSCFG GD32_CLOCK_CONFIG(APB2EN, 14U)
102 0 : #define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 16U)
103 0 : #define GD32_CLOCK_TIMER9 GD32_CLOCK_CONFIG(APB2EN, 17U)
104 0 : #define GD32_CLOCK_TIMER10 GD32_CLOCK_CONFIG(APB2EN, 18U)
105 0 : #define GD32_CLOCK_SPI4 GD32_CLOCK_CONFIG(APB2EN, 20U)
106 0 : #define GD32_CLOCK_SPI5 GD32_CLOCK_CONFIG(APB2EN, 21U)
107 0 : #define GD32_CLOCK_TLI GD32_CLOCK_CONFIG(APB2EN, 26U)
108 :
109 : /* APB1 additional peripherals */
110 0 : #define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)
111 0 : #define GD32_CLOCK_IREF GD32_CLOCK_CONFIG(ADDAPB1EN, 31U)
112 :
113 : /** @} */
114 :
115 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_ */
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