Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2022 BrainCo.
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32L23X_CLOCKS_H_
       8             : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32L23X_CLOCKS_H_
       9             : 
      10             : #include "gd32-clocks-common.h"
      11             : 
      12             : /**
      13             :  * @name Register offsets
      14             :  * @{
      15             :  */
      16             : 
      17           0 : #define GD32_AHB1EN_OFFSET       0x14U
      18           0 : #define GD32_APB1EN_OFFSET       0x1CU
      19           0 : #define GD32_APB2EN_OFFSET       0x18U
      20             : 
      21             : /** @} */
      22             : 
      23             : /**
      24             :  * @name Clock enable/disable definitions for peripherals
      25             :  * @{
      26             :  */
      27             : 
      28             : /* AHB1 peripherals */
      29           0 : #define GD32_CLOCK_DMA        GD32_CLOCK_CONFIG(AHB1EN, 0U)
      30           0 : #define GD32_CLOCK_SRAM0      GD32_CLOCK_CONFIG(AHB1EN, 2U)
      31           0 : #define GD32_CLOCK_FMC        GD32_CLOCK_CONFIG(AHB1EN, 4U)
      32           0 : #define GD32_CLOCK_CRC        GD32_CLOCK_CONFIG(AHB1EN, 6U)
      33           0 : #define GD32_CLOCK_SRAM1      GD32_CLOCK_CONFIG(AHB1EN, 7U)
      34           0 : #define GD32_CLOCK_GPIOA      GD32_CLOCK_CONFIG(AHB1EN, 17U)
      35           0 : #define GD32_CLOCK_GPIOB      GD32_CLOCK_CONFIG(AHB1EN, 18U)
      36           0 : #define GD32_CLOCK_GPIOC      GD32_CLOCK_CONFIG(AHB1EN, 19U)
      37           0 : #define GD32_CLOCK_GPIOD      GD32_CLOCK_CONFIG(AHB1EN, 20U)
      38           0 : #define GD32_CLOCK_GPIOF      GD32_CLOCK_CONFIG(AHB1EN, 22U)
      39             : 
      40             : /* AHB2 peripherals */
      41           0 : #define GD32_CLOCK_CAU        GD32_CLOCK_CONFIG(AHB2EN, 1U)
      42           0 : #define GD32_CLOCK_TRNG       GD32_CLOCK_CONFIG(AHB2EN, 3U)
      43             : 
      44             : /* APB1 peripherals */
      45           0 : #define GD32_CLOCK_TIMER1     GD32_CLOCK_CONFIG(APB1EN, 0U)
      46           0 : #define GD32_CLOCK_TIMER2     GD32_CLOCK_CONFIG(APB1EN, 1U)
      47           0 : #define GD32_CLOCK_TIMER5     GD32_CLOCK_CONFIG(APB1EN, 4U)
      48           0 : #define GD32_CLOCK_TIMER6     GD32_CLOCK_CONFIG(APB1EN, 5U)
      49           0 : #define GD32_CLOCK_TIMER11    GD32_CLOCK_CONFIG(APB1EN, 8U)
      50           0 : #define GD32_CLOCK_LPTIMER    GD32_CLOCK_CONFIG(APB1EN, 9U)
      51           0 : #define GD32_CLOCK_SLCD       GD32_CLOCK_CONFIG(APB1EN, 10U)
      52           0 : #define GD32_CLOCK_WWDGT      GD32_CLOCK_CONFIG(APB1EN, 11U)
      53           0 : #define GD32_CLOCK_SPI1       GD32_CLOCK_CONFIG(APB1EN, 14U)
      54           0 : #define GD32_CLOCK_USART1     GD32_CLOCK_CONFIG(APB1EN, 17U)
      55           0 : #define GD32_CLOCK_LPUART     GD32_CLOCK_CONFIG(APB1EN, 18U)
      56           0 : #define GD32_CLOCK_UART3      GD32_CLOCK_CONFIG(APB1EN, 19U)
      57           0 : #define GD32_CLOCK_UART4      GD32_CLOCK_CONFIG(APB1EN, 20U)
      58           0 : #define GD32_CLOCK_I2C0       GD32_CLOCK_CONFIG(APB1EN, 21U)
      59           0 : #define GD32_CLOCK_I2C1       GD32_CLOCK_CONFIG(APB1EN, 22U)
      60           0 : #define GD32_CLOCK_USBD       GD32_CLOCK_CONFIG(APB1EN, 23U)
      61           0 : #define GD32_CLOCK_I2C2       GD32_CLOCK_CONFIG(APB1EN, 24U)
      62           0 : #define GD32_CLOCK_PMU        GD32_CLOCK_CONFIG(APB1EN, 28U)
      63           0 : #define GD32_CLOCK_DAC        GD32_CLOCK_CONFIG(APB1EN, 29U)
      64           0 : #define GD32_CLOCK_CTC        GD32_CLOCK_CONFIG(APB1EN, 30U)
      65           0 : #define GD32_CLOCK_BKP        GD32_CLOCK_CONFIG(APB1EN, 31U)
      66             : 
      67             : /* APB2 peripherals */
      68           0 : #define GD32_CLOCK_SYSCFG     GD32_CLOCK_CONFIG(APB2EN, 0U)
      69           0 : #define GD32_CLOCK_CMP        GD32_CLOCK_CONFIG(APB2EN, 1U)
      70           0 : #define GD32_CLOCK_ADC        GD32_CLOCK_CONFIG(APB2EN, 9U)
      71           0 : #define GD32_CLOCK_TIMER8     GD32_CLOCK_CONFIG(APB2EN, 11U)
      72           0 : #define GD32_CLOCK_SPI0       GD32_CLOCK_CONFIG(APB2EN, 12U)
      73           0 : #define GD32_CLOCK_USART0     GD32_CLOCK_CONFIG(APB2EN, 14U)
      74           0 : #define GD32_CLOCK_DBGMCU     GD32_CLOCK_CONFIG(APB2EN, 22U)
      75             : 
      76             : /** @} */
      77             : 
      78             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_ */