Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Infineon Technologies AG,
3 : * or an affiliate of Infineon Technologies AG.
4 : *
5 : * SPDX-License-Identifier: Apache-2.0
6 : */
7 :
8 0 : #define CLK_SOURCE_IHO
9 0 : #define CLK_SOURCE_PILO
10 :
11 1 : #define IFX_IHO 1 /*!< Internal High Speed Oscillator Input Clock */
12 1 : #define IFX_IMO 2 /*!< Internal Main Oscillator Input Clock */
13 1 : #define IFX_ECO 3 /*!< External Crystal Oscillator Input Clock */
14 1 : #define IFX_EXT 4 /*!< External Input Clock */
15 1 : #define IFX_ALTHF 5 /*!< Alternate High Frequency Input Clock */
16 1 : #define IFX_ALTLF 6 /*!< Alternate Low Frequency Input Clock */
17 1 : #define IFX_ILO 7 /*!< Internal Low Speed Oscillator Input Clock */
18 1 : #define IFX_PILO 8 /*!< Precision ILO Input Clock */
19 1 : #define IFX_WCO 9 /*!< Watch Crystal Oscillator Input Clock */
20 1 : #define IFX_MFO 10 /*!< Medium Frequency Oscillator Clock */
21 1 : #define IFX_PATHMUX 11 /*!< Path selection mux for input to FLL/PLLs */
22 1 : #define IFX_FLL 12 /*!< Frequency-Locked Loop Clock */
23 1 : #define IFX_PLL200 13 /*!< 200MHz Phase-Locked Loop Clock */
24 1 : #define IFX_PLL400 14 /*!< 400MHz Phase-Locked Loop Clock */
25 1 : #define IFX_ECO_PRESCALER 15 /*!< ECO Prescaler Divider */
26 1 : #define IFX_LF 16 /*!< Low Frequency Clock */
27 1 : #define IFX_MF 17 /*!< Medium Frequency Clock */
28 1 : #define IFX_HF 18 /*!< High Frequency Clock */
29 1 : #define IFX_PUMP 19 /*!< Analog Pump Clock */
30 1 : #define IFX_BAK 20 /*!< Backup Power Domain Clock */
31 1 : #define IFX_ALT_SYS_TICK 21 /*!< Alternative SysTick Clock */
32 1 : #define IFX_PERI 22 /*!< Peripheral Clock Group */
33 1 : #define IFX_DPLL250_0 23 /*!< 250MHz Digital Phase-Locked Loop Clock 0 */
34 1 : #define IFX_DPLL250_1 24 /*!< 250MHz Digital Phase-Locked Loop Clock 1 */
35 1 : #define IFX_DPLL500 25 /*!< 500MHz Digital Phase-Locked Loop Clock */
36 :
37 1 : #define IFX_CLK_HF_NO_DIVIDE 0 /**< don't divide clkHf */
38 1 : #define IFX_CLK_HF_DIVIDE_BY_2 1 /**< divide clkHf by 2 */
39 1 : #define IFX_CLK_HF_DIVIDE_BY_3 2 /**< divide clkHf by 3 */
40 1 : #define IFX_CLK_HF_DIVIDE_BY_4 3 /**< divide clkHf by 4 */
41 1 : #define IFX_CLK_HF_DIVIDE_BY_5 4 /**< divide clkHf by 5 */
42 1 : #define IFX_CLK_HF_DIVIDE_BY_6 5 /**< divide clkHf by 6 */
43 1 : #define IFX_CLK_HF_DIVIDE_BY_7 6 /**< divide clkHf by 7 */
44 1 : #define IFX_CLK_HF_DIVIDE_BY_8 7 /**< divide clkHf by 8 */
45 1 : #define IFX_CLK_HF_DIVIDE_BY_9 8 /**< divide clkHf by 9 */
46 1 : #define IFX_CLK_HF_DIVIDE_BY_10 9 /**< divide clkHf by 10 */
47 1 : #define IFX_CLK_HF_DIVIDE_BY_11 10 /**< divide clkHf by 11 */
48 1 : #define IFX_CLK_HF_DIVIDE_BY_12 11 /**< divide clkHf by 12 */
49 1 : #define IFX_CLK_HF_DIVIDE_BY_13 12 /**< divide clkHf by 13 */
50 1 : #define IFX_CLK_HF_DIVIDE_BY_14 13 /**< divide clkHf by 14 */
51 1 : #define IFX_CLK_HF_DIVIDE_BY_15 14 /**< divide clkHf by 15 */
52 1 : #define IFX_CLK_HF_DIVIDE_BY_16 15 /**< divide clkHf by 16 */
53 1 : #define IFX_CLK_HF_MAX_DIVIDER /**< Max divider */
54 :
55 : /* Target resource types for peripheral dividers */
56 1 : #define IFX_RSC_ADC 0 /*!< Analog to digital converter */
57 1 : #define IFX_RSC_ADCMIC 1 /*!< Analog to digital converter with Analog Mic support */
58 1 : #define IFX_RSC_BLESS 2 /*!< Bluetooth communications block */
59 1 : #define IFX_RSC_CAN 3 /*!< CAN communication block */
60 1 : #define IFX_RSC_CLKPATH 4 /*!< Clock Path. DEPRECATED. */
61 1 : #define IFX_RSC_CLOCK 5 /*!< Clock */
62 1 : #define IFX_RSC_CRYPTO 6 /*!< Crypto hardware accelerator */
63 1 : #define IFX_RSC_DAC 7 /*!< Digital to analog converter */
64 1 : #define IFX_RSC_DMA 8 /*!< DMA controller */
65 1 : #define IFX_RSC_DW 9 /*!< Datawire DMA controller */
66 1 : #define IFX_RSC_ETH 10 /*!< Ethernet communications block */
67 1 : #define IFX_RSC_GPIO 11 /*!< General purpose I/O pin */
68 1 : #define IFX_RSC_I2S 12 /*!< I2S communications block */
69 1 : #define IFX_RSC_I3C 13 /*!< I3C communications block */
70 1 : #define IFX_RSC_KEYSCAN 14 /*!< KeyScan block */
71 1 : #define IFX_RSC_LCD 15 /*!< Segment LCD controller */
72 1 : #define IFX_RSC_LIN 16 /*!< LIN communications block */
73 1 : #define IFX_RSC_LPCOMP 17 /*!< Low power comparator */
74 1 : #define IFX_RSC_LPTIMER 18 /*!< Low power timer */
75 1 : #define IFX_RSC_OPAMP 19 /*!< Opamp */
76 1 : #define IFX_RSC_PDM 20 /*!< PCM/PDM communications block */
77 1 : #define IFX_RSC_PTC 21 /*!< Programmable Threshold comparator */
78 1 : #define IFX_RSC_SMIF 22 /*!< Quad-SPI communications block */
79 1 : #define IFX_RSC_RTC 23 /*!< Real time clock */
80 1 : #define IFX_RSC_SCB 24 /*!< Serial Communications Block */
81 1 : #define IFX_RSC_SDHC 25 /*!< SD Host Controller */
82 1 : #define IFX_RSC_SDIODEV 26 /*!< SDIO Device Block */
83 1 : #define IFX_RSC_TCPWM 27 /*!< Timer/Counter/PWM block */
84 1 : #define IFX_RSC_TDM 28 /*!< TDM block */
85 1 : #define IFX_RSC_UDB 29 /*!< UDB Array */
86 1 : #define IFX_RSC_USB 30 /*!< USB communication block */
87 1 : #define IFX_RSC_INVALID 31 /*!< Placeholder for invalid type */
|
