Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3 : * an affiliate of Cypress Semiconductor Corporation
4 : *
5 : * SPDX-License-Identifier: Apache-2.0
6 : */
7 :
8 0 : #define CLK_SOURCE_IHO
9 0 : #define CLK_SOURCE_PILO
10 :
11 1 : #define IFX_CAT1_CLOCK_BLOCK_IHO 1 /*!< Internal High Speed Oscillator Input Clock */
12 1 : #define IFX_CAT1_CLOCK_BLOCK_IMO 2 /*!< Internal Main Oscillator Input Clock */
13 1 : #define IFX_CAT1_CLOCK_BLOCK_ECO 3 /*!< External Crystal Oscillator Input Clock */
14 1 : #define IFX_CAT1_CLOCK_BLOCK_EXT 4 /*!< External Input Clock */
15 1 : #define IFX_CAT1_CLOCK_BLOCK_ALTHF 5 /*!< Alternate High Frequency Input Clock */
16 1 : #define IFX_CAT1_CLOCK_BLOCK_ALTLF 6 /*!< Alternate Low Frequency Input Clock */
17 1 : #define IFX_CAT1_CLOCK_BLOCK_ILO 7 /*!< Internal Low Speed Oscillator Input Clock */
18 1 : #define IFX_CAT1_CLOCK_BLOCK_PILO 8 /*!< Precision ILO Input Clock */
19 1 : #define IFX_CAT1_CLOCK_BLOCK_WCO 9 /*!< Watch Crystal Oscillator Input Clock */
20 1 : #define IFX_CAT1_CLOCK_BLOCK_MFO 10 /*!< Medium Frequency Oscillator Clock */
21 :
22 1 : #define IFX_CAT1_CLOCK_BLOCK_PATHMUX 11 /*!< Path selection mux for input to FLL/PLLs */
23 :
24 1 : #define IFX_CAT1_CLOCK_BLOCK_FLL 12 /*!< Frequency-Locked Loop Clock */
25 1 : #define IFX_CAT1_CLOCK_BLOCK_PLL200 13 /*!< 200MHz Phase-Locked Loop Clock */
26 1 : #define IFX_CAT1_CLOCK_BLOCK_PLL400 14 /*!< 400MHz Phase-Locked Loop Clock */
27 1 : #define IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER 15 /*!< ECO Prescaler Divider */
28 :
29 1 : #define IFX_CAT1_CLOCK_BLOCK_LF 16 /*!< Low Frequency Clock */
30 1 : #define IFX_CAT1_CLOCK_BLOCK_MF 17 /*!< Medium Frequency Clock */
31 1 : #define IFX_CAT1_CLOCK_BLOCK_HF 18 /*!< High Frequency Clock */
32 :
33 1 : #define IFX_CAT1_CLOCK_BLOCK_PUMP 19 /*!< Analog Pump Clock */
34 1 : #define IFX_CAT1_CLOCK_BLOCK_BAK 20 /*!< Backup Power Domain Clock */
35 1 : #define IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK 21 /*!< Alternative SysTick Clock */
36 1 : #define IFX_CAT1_CLOCK_BLOCK_PERI 22 /*!< Peripheral Clock Group */
37 :
38 1 : #define IFX_CAT1_CLKHF_NO_DIVIDE 0 /**< don't divide clkHf */
39 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_2 1 /**< divide clkHf by 2 */
40 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_3 2 /**< divide clkHf by 3 */
41 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_4 3 /**< divide clkHf by 4 */
42 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_5 4 /**< divide clkHf by 5 */
43 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_6 5 /**< divide clkHf by 6 */
44 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_7 6 /**< divide clkHf by 7 */
45 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_8 7 /**< divide clkHf by 8 */
46 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_9 8 /**< divide clkHf by 9 */
47 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_10 9 /**< divide clkHf by 10 */
48 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_11 10 /**< divide clkHf by 11 */
49 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_12 11 /**< divide clkHf by 12 */
50 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_13 12 /**< divide clkHf by 13 */
51 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_14 13 /**< divide clkHf by 14 */
52 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_15 14 /**< divide clkHf by 15 */
53 1 : #define IFX_CAT1_CLKHF_DIVIDE_BY_16 15 /**< divide clkHf by 16 */
54 1 : #define IFX_CAT1_CLKHF_MAX_DIVIDER /**< Max divider */
55 :
56 1 : #define IFX_CAT1_CLKPATH_IN_IMO 0 /**< Select the IMO as the output of the path mux */
57 1 : #define IFX_CAT1_CLKPATH_IN_EXT 1 /**< Select the EXT as the output of the path mux */
58 1 : #define IFX_CAT1_CLKPATH_IN_ECO 2 /**< Select the ECO as the output of the path mux */
59 1 : #define IFX_CAT1_CLKPATH_IN_ALTHF 3 /**< Select the ALTHF as the output of the path mux */
60 : /* Select the DSI MUX output as the output of the path mux */
61 0 : #define IFX_CAT1_CLKPATH_IN_DSIMUX 4
62 1 : #define IFX_CAT1_CLKPATH_IN_LPECO 5 /**< Select the LPECO as the output of the path mux */
63 1 : #define IFX_CAT1_CLKPATH_IN_IHO 6 /**< Select the IHO as the output of the path mux */
64 : /* Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. \
65 : * Make sure the DSI clock sources are available on used device. \
66 : */
67 1 : #define IFX_CAT1_CLKPATH_IN_DSI 0x100
68 : /**< Select the ILO (16) as the output of the DSI mux and path mux */
69 1 : #define IFX_CAT1_CLKPATH_IN_ILO 0x110
70 : /**< Select the WCO (17) as the output of the DSI mux and path mux */
71 1 : #define IFX_CAT1_CLKPATH_IN_WCO 0x111
72 : /**< Select the ALTLF (18) as the output of the DSI mux and path mux. \
73 : * Make sure the ALTLF clock sources in available on used device. \
74 : */
75 1 : #define IFX_CAT1_CLKPATH_IN_ALTLF 0x112
76 : /**< Select the PILO (19) as the output of the DSI mux and path mux. \
77 : * Make sure the PILO clock sources in available on used device. \
78 : */
79 1 : #define IFX_CAT1_CLKPATH_IN_PILO 0x113
80 : /**< Select the ILO1 (20) as the output of the DSI mux and path mux */
81 0 : #define IFX_CAT1_CLKPATH_IN_ILO1 0x114
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