Line data Source code
1 0 : /*
2 : * Copyright 2024 NXP
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX95_CLOCK_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX95_CLOCK_H_
9 :
10 0 : #define IMX95_CLK_32K 1
11 0 : #define IMX95_CLK_24M 2
12 0 : #define IMX95_CLK_FRO 3
13 0 : #define IMX95_CLK_SYSPLL1_VCO 4
14 0 : #define IMX95_CLK_SYSPLL1_PFD0_UNGATED 5
15 0 : #define IMX95_CLK_SYSPLL1_PFD0 6
16 0 : #define IMX95_CLK_SYSPLL1_PFD0_DIV2 7
17 0 : #define IMX95_CLK_SYSPLL1_PFD1_UNGATED 8
18 0 : #define IMX95_CLK_SYSPLL1_PFD1 9
19 0 : #define IMX95_CLK_SYSPLL1_PFD1_DIV2 10
20 0 : #define IMX95_CLK_SYSPLL1_PFD2_UNGATED 11
21 0 : #define IMX95_CLK_SYSPLL1_PFD2 12
22 0 : #define IMX95_CLK_SYSPLL1_PFD2_DIV2 13
23 0 : #define IMX95_CLK_AUDIOPLL1_VCO 14
24 0 : #define IMX95_CLK_AUDIOPLL1 15
25 0 : #define IMX95_CLK_AUDIOPLL2_VCO 16
26 0 : #define IMX95_CLK_AUDIOPLL2 17
27 0 : #define IMX95_CLK_VIDEOPLL1_VCO 18
28 0 : #define IMX95_CLK_VIDEOPLL1 19
29 0 : #define IMX95_CLK_RESERVED20 20
30 0 : #define IMX95_CLK_RESERVED21 21
31 0 : #define IMX95_CLK_RESERVED22 22
32 0 : #define IMX95_CLK_RESERVED23 23
33 0 : #define IMX95_CLK_ARMPLL_VCO 24
34 0 : #define IMX95_CLK_ARMPLL_PFD0_UNGATED 25
35 0 : #define IMX95_CLK_ARMPLL_PFD0 26
36 0 : #define IMX95_CLK_ARMPLL_PFD1_UNGATED 27
37 0 : #define IMX95_CLK_ARMPLL_PFD1 28
38 0 : #define IMX95_CLK_ARMPLL_PFD2_UNGATED 29
39 0 : #define IMX95_CLK_ARMPLL_PFD2 30
40 0 : #define IMX95_CLK_ARMPLL_PFD3_UNGATED 31
41 0 : #define IMX95_CLK_ARMPLL_PFD3 32
42 0 : #define IMX95_CLK_DRAMPLL_VCO 33
43 0 : #define IMX95_CLK_DRAMPLL 34
44 0 : #define IMX95_CLK_HSIOPLL_VCO 35
45 0 : #define IMX95_CLK_HSIOPLL 36
46 0 : #define IMX95_CLK_LDBPLL_VCO 37
47 0 : #define IMX95_CLK_LDBPLL 38
48 0 : #define IMX95_CLK_EXT1 39
49 0 : #define IMX95_CLK_EXT2 40
50 :
51 0 : #define IMX95_CCM_NUM_CLK_SRC 41
52 :
53 0 : #define IMX95_CLK_ADC (IMX95_CCM_NUM_CLK_SRC + 0)
54 0 : #define IMX95_CLK_TMU (IMX95_CCM_NUM_CLK_SRC + 1)
55 0 : #define IMX95_CLK_BUSAON (IMX95_CCM_NUM_CLK_SRC + 2)
56 0 : #define IMX95_CLK_CAN1 (IMX95_CCM_NUM_CLK_SRC + 3)
57 0 : #define IMX95_CLK_I3C1 (IMX95_CCM_NUM_CLK_SRC + 4)
58 0 : #define IMX95_CLK_I3C1SLOW (IMX95_CCM_NUM_CLK_SRC + 5)
59 0 : #define IMX95_CLK_LPI2C1 (IMX95_CCM_NUM_CLK_SRC + 6)
60 0 : #define IMX95_CLK_LPI2C2 (IMX95_CCM_NUM_CLK_SRC + 7)
61 0 : #define IMX95_CLK_LPSPI1 (IMX95_CCM_NUM_CLK_SRC + 8)
62 0 : #define IMX95_CLK_LPSPI2 (IMX95_CCM_NUM_CLK_SRC + 9)
63 0 : #define IMX95_CLK_LPTMR1 (IMX95_CCM_NUM_CLK_SRC + 10)
64 0 : #define IMX95_CLK_LPUART1 (IMX95_CCM_NUM_CLK_SRC + 11)
65 0 : #define IMX95_CLK_LPUART2 (IMX95_CCM_NUM_CLK_SRC + 12)
66 0 : #define IMX95_CLK_M33 (IMX95_CCM_NUM_CLK_SRC + 13)
67 0 : #define IMX95_CLK_M33SYSTICK (IMX95_CCM_NUM_CLK_SRC + 14)
68 0 : #define IMX95_CLK_MQS1 (IMX95_CCM_NUM_CLK_SRC + 15)
69 0 : #define IMX95_CLK_PDM (IMX95_CCM_NUM_CLK_SRC + 16)
70 0 : #define IMX95_CLK_SAI1 (IMX95_CCM_NUM_CLK_SRC + 17)
71 0 : #define IMX95_CLK_SENTINEL (IMX95_CCM_NUM_CLK_SRC + 18)
72 0 : #define IMX95_CLK_TPM2 (IMX95_CCM_NUM_CLK_SRC + 19)
73 0 : #define IMX95_CLK_TSTMR1 (IMX95_CCM_NUM_CLK_SRC + 20)
74 0 : #define IMX95_CLK_CAMAPB (IMX95_CCM_NUM_CLK_SRC + 21)
75 0 : #define IMX95_CLK_CAMAXI (IMX95_CCM_NUM_CLK_SRC + 22)
76 0 : #define IMX95_CLK_CAMCM0 (IMX95_CCM_NUM_CLK_SRC + 23)
77 0 : #define IMX95_CLK_CAMISI (IMX95_CCM_NUM_CLK_SRC + 24)
78 0 : #define IMX95_CLK_MIPIPHYCFG (IMX95_CCM_NUM_CLK_SRC + 25)
79 0 : #define IMX95_CLK_MIPIPHYPLLBYPASS (IMX95_CCM_NUM_CLK_SRC + 26)
80 0 : #define IMX95_CLK_MIPIPHYPLLREF (IMX95_CCM_NUM_CLK_SRC + 27)
81 0 : #define IMX95_CLK_MIPITESTBYTE (IMX95_CCM_NUM_CLK_SRC + 28)
82 0 : #define IMX95_CLK_A55 (IMX95_CCM_NUM_CLK_SRC + 29)
83 0 : #define IMX95_CLK_A55MTRBUS (IMX95_CCM_NUM_CLK_SRC + 30)
84 0 : #define IMX95_CLK_A55PERIPH (IMX95_CCM_NUM_CLK_SRC + 31)
85 0 : #define IMX95_CLK_DRAMALT (IMX95_CCM_NUM_CLK_SRC + 32)
86 0 : #define IMX95_CLK_DRAMAPB (IMX95_CCM_NUM_CLK_SRC + 33)
87 0 : #define IMX95_CLK_DISPAPB (IMX95_CCM_NUM_CLK_SRC + 34)
88 0 : #define IMX95_CLK_DISPAXI (IMX95_CCM_NUM_CLK_SRC + 35)
89 0 : #define IMX95_CLK_DISPDP (IMX95_CCM_NUM_CLK_SRC + 36)
90 0 : #define IMX95_CLK_DISPOCRAM (IMX95_CCM_NUM_CLK_SRC + 37)
91 0 : #define IMX95_CLK_DISPUSB31 (IMX95_CCM_NUM_CLK_SRC + 38)
92 0 : #define IMX95_CLK_DISP1PIX (IMX95_CCM_NUM_CLK_SRC + 39)
93 0 : #define IMX95_CLK_DISP2PIX (IMX95_CCM_NUM_CLK_SRC + 40)
94 0 : #define IMX95_CLK_DISP3PIX (IMX95_CCM_NUM_CLK_SRC + 41)
95 0 : #define IMX95_CLK_GPUAPB (IMX95_CCM_NUM_CLK_SRC + 42)
96 0 : #define IMX95_CLK_GPU (IMX95_CCM_NUM_CLK_SRC + 43)
97 0 : #define IMX95_CLK_HSIOACSCAN480M (IMX95_CCM_NUM_CLK_SRC + 44)
98 0 : #define IMX95_CLK_HSIOACSCAN80M (IMX95_CCM_NUM_CLK_SRC + 45)
99 0 : #define IMX95_CLK_HSIO (IMX95_CCM_NUM_CLK_SRC + 46)
100 0 : #define IMX95_CLK_HSIOPCIEAUX (IMX95_CCM_NUM_CLK_SRC + 47)
101 0 : #define IMX95_CLK_HSIOPCIETEST160M (IMX95_CCM_NUM_CLK_SRC + 48)
102 0 : #define IMX95_CLK_HSIOPCIETEST400M (IMX95_CCM_NUM_CLK_SRC + 49)
103 0 : #define IMX95_CLK_HSIOPCIETEST500M (IMX95_CCM_NUM_CLK_SRC + 50)
104 0 : #define IMX95_CLK_HSIOUSBTEST50M (IMX95_CCM_NUM_CLK_SRC + 51)
105 0 : #define IMX95_CLK_HSIOUSBTEST60M (IMX95_CCM_NUM_CLK_SRC + 52)
106 0 : #define IMX95_CLK_BUSM7 (IMX95_CCM_NUM_CLK_SRC + 53)
107 0 : #define IMX95_CLK_M7 (IMX95_CCM_NUM_CLK_SRC + 54)
108 0 : #define IMX95_CLK_M7SYSTICK (IMX95_CCM_NUM_CLK_SRC + 55)
109 0 : #define IMX95_CLK_BUSNETCMIX (IMX95_CCM_NUM_CLK_SRC + 56)
110 0 : #define IMX95_CLK_ENET (IMX95_CCM_NUM_CLK_SRC + 57)
111 0 : #define IMX95_CLK_ENETPHYTEST200M (IMX95_CCM_NUM_CLK_SRC + 58)
112 0 : #define IMX95_CLK_ENETPHYTEST500M (IMX95_CCM_NUM_CLK_SRC + 59)
113 0 : #define IMX95_CLK_ENETPHYTEST667M (IMX95_CCM_NUM_CLK_SRC + 60)
114 0 : #define IMX95_CLK_ENETREF (IMX95_CCM_NUM_CLK_SRC + 61)
115 0 : #define IMX95_CLK_ENETTIMER1 (IMX95_CCM_NUM_CLK_SRC + 62)
116 0 : #define IMX95_CLK_MQS2 (IMX95_CCM_NUM_CLK_SRC + 63)
117 0 : #define IMX95_CLK_SAI2 (IMX95_CCM_NUM_CLK_SRC + 64)
118 0 : #define IMX95_CLK_NOCAPB (IMX95_CCM_NUM_CLK_SRC + 65)
119 0 : #define IMX95_CLK_NOC (IMX95_CCM_NUM_CLK_SRC + 66)
120 0 : #define IMX95_CLK_NPUAPB (IMX95_CCM_NUM_CLK_SRC + 67)
121 0 : #define IMX95_CLK_NPU (IMX95_CCM_NUM_CLK_SRC + 68)
122 0 : #define IMX95_CLK_CCMCKO1 (IMX95_CCM_NUM_CLK_SRC + 69)
123 0 : #define IMX95_CLK_CCMCKO2 (IMX95_CCM_NUM_CLK_SRC + 70)
124 0 : #define IMX95_CLK_CCMCKO3 (IMX95_CCM_NUM_CLK_SRC + 71)
125 0 : #define IMX95_CLK_CCMCKO4 (IMX95_CCM_NUM_CLK_SRC + 72)
126 0 : #define IMX95_CLK_VPUAPB (IMX95_CCM_NUM_CLK_SRC + 73)
127 0 : #define IMX95_CLK_VPU (IMX95_CCM_NUM_CLK_SRC + 74)
128 0 : #define IMX95_CLK_VPUDSP (IMX95_CCM_NUM_CLK_SRC + 75)
129 0 : #define IMX95_CLK_VPUJPEG (IMX95_CCM_NUM_CLK_SRC + 76)
130 0 : #define IMX95_CLK_AUDIOXCVR (IMX95_CCM_NUM_CLK_SRC + 77)
131 0 : #define IMX95_CLK_BUSWAKEUP (IMX95_CCM_NUM_CLK_SRC + 78)
132 0 : #define IMX95_CLK_CAN2 (IMX95_CCM_NUM_CLK_SRC + 79)
133 0 : #define IMX95_CLK_CAN3 (IMX95_CCM_NUM_CLK_SRC + 80)
134 0 : #define IMX95_CLK_CAN4 (IMX95_CCM_NUM_CLK_SRC + 81)
135 0 : #define IMX95_CLK_CAN5 (IMX95_CCM_NUM_CLK_SRC + 82)
136 0 : #define IMX95_CLK_FLEXIO1 (IMX95_CCM_NUM_CLK_SRC + 83)
137 0 : #define IMX95_CLK_FLEXIO2 (IMX95_CCM_NUM_CLK_SRC + 84)
138 0 : #define IMX95_CLK_FLEXSPI1 (IMX95_CCM_NUM_CLK_SRC + 85)
139 0 : #define IMX95_CLK_I3C2 (IMX95_CCM_NUM_CLK_SRC + 86)
140 0 : #define IMX95_CLK_I3C2SLOW (IMX95_CCM_NUM_CLK_SRC + 87)
141 0 : #define IMX95_CLK_LPI2C3 (IMX95_CCM_NUM_CLK_SRC + 88)
142 0 : #define IMX95_CLK_LPI2C4 (IMX95_CCM_NUM_CLK_SRC + 89)
143 0 : #define IMX95_CLK_LPI2C5 (IMX95_CCM_NUM_CLK_SRC + 90)
144 0 : #define IMX95_CLK_LPI2C6 (IMX95_CCM_NUM_CLK_SRC + 91)
145 0 : #define IMX95_CLK_LPI2C7 (IMX95_CCM_NUM_CLK_SRC + 92)
146 0 : #define IMX95_CLK_LPI2C8 (IMX95_CCM_NUM_CLK_SRC + 93)
147 0 : #define IMX95_CLK_LPSPI3 (IMX95_CCM_NUM_CLK_SRC + 94)
148 0 : #define IMX95_CLK_LPSPI4 (IMX95_CCM_NUM_CLK_SRC + 95)
149 0 : #define IMX95_CLK_LPSPI5 (IMX95_CCM_NUM_CLK_SRC + 96)
150 0 : #define IMX95_CLK_LPSPI6 (IMX95_CCM_NUM_CLK_SRC + 97)
151 0 : #define IMX95_CLK_LPSPI7 (IMX95_CCM_NUM_CLK_SRC + 98)
152 0 : #define IMX95_CLK_LPSPI8 (IMX95_CCM_NUM_CLK_SRC + 99)
153 0 : #define IMX95_CLK_LPTMR2 (IMX95_CCM_NUM_CLK_SRC + 100)
154 0 : #define IMX95_CLK_LPUART3 (IMX95_CCM_NUM_CLK_SRC + 101)
155 0 : #define IMX95_CLK_LPUART4 (IMX95_CCM_NUM_CLK_SRC + 102)
156 0 : #define IMX95_CLK_LPUART5 (IMX95_CCM_NUM_CLK_SRC + 103)
157 0 : #define IMX95_CLK_LPUART6 (IMX95_CCM_NUM_CLK_SRC + 104)
158 0 : #define IMX95_CLK_LPUART7 (IMX95_CCM_NUM_CLK_SRC + 105)
159 0 : #define IMX95_CLK_LPUART8 (IMX95_CCM_NUM_CLK_SRC + 106)
160 0 : #define IMX95_CLK_SAI3 (IMX95_CCM_NUM_CLK_SRC + 107)
161 0 : #define IMX95_CLK_SAI4 (IMX95_CCM_NUM_CLK_SRC + 108)
162 0 : #define IMX95_CLK_SAI5 (IMX95_CCM_NUM_CLK_SRC + 109)
163 0 : #define IMX95_CLK_SPDIF (IMX95_CCM_NUM_CLK_SRC + 110)
164 0 : #define IMX95_CLK_SWOTRACE (IMX95_CCM_NUM_CLK_SRC + 111)
165 0 : #define IMX95_CLK_TPM4 (IMX95_CCM_NUM_CLK_SRC + 112)
166 0 : #define IMX95_CLK_TPM5 (IMX95_CCM_NUM_CLK_SRC + 113)
167 0 : #define IMX95_CLK_TPM6 (IMX95_CCM_NUM_CLK_SRC + 114)
168 0 : #define IMX95_CLK_TSTMR2 (IMX95_CCM_NUM_CLK_SRC + 115)
169 0 : #define IMX95_CLK_USBPHYBURUNIN (IMX95_CCM_NUM_CLK_SRC + 116)
170 0 : #define IMX95_CLK_USDHC1 (IMX95_CCM_NUM_CLK_SRC + 117)
171 0 : #define IMX95_CLK_USDHC2 (IMX95_CCM_NUM_CLK_SRC + 118)
172 0 : #define IMX95_CLK_USDHC3 (IMX95_CCM_NUM_CLK_SRC + 119)
173 0 : #define IMX95_CLK_V2XPK (IMX95_CCM_NUM_CLK_SRC + 120)
174 0 : #define IMX95_CLK_WAKEUPAXI (IMX95_CCM_NUM_CLK_SRC + 121)
175 0 : #define IMX95_CLK_XSPISLVROOT (IMX95_CCM_NUM_CLK_SRC + 122)
176 :
177 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX95_CLOCK_H_ */
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