Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2019 Vestas Wind Systems A/S
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_
       8             : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_
       9             : 
      10             : /* SCG system oscillator mode */
      11           0 : #define KINETIS_SCG_SOSC_MODE_EXT        0U
      12           0 : #define KINETIS_SCG_SOSC_MODE_LOW_POWER  4U
      13           0 : #define KINETIS_SCG_SOSC_MODE_HIGH_GAIN 12U
      14             : 
      15             : /* SCG clock controller clock names */
      16           0 : #define KINETIS_SCG_CORESYS_CLK          0U
      17           0 : #define KINETIS_SCG_BUS_CLK              1U
      18           0 : #define KINETIS_SCG_FLEXBUS_CLK          2U
      19           0 : #define KINETIS_SCG_FLASH_CLK            3U
      20           0 : #define KINETIS_SCG_SOSC_CLK             4U
      21           0 : #define KINETIS_SCG_SIRC_CLK             5U
      22           0 : #define KINETIS_SCG_FIRC_CLK             6U
      23           0 : #define KINETIS_SCG_SPLL_CLK             7U
      24           0 : #define KINETIS_SCG_SOSC_ASYNC_DIV1_CLK  8U
      25           0 : #define KINETIS_SCG_SOSC_ASYNC_DIV2_CLK  9U
      26           0 : #define KINETIS_SCG_SIRC_ASYNC_DIV1_CLK 10U
      27           0 : #define KINETIS_SCG_SIRC_ASYNC_DIV2_CLK 11U
      28           0 : #define KINETIS_SCG_FIRC_ASYNC_DIV1_CLK 12U
      29           0 : #define KINETIS_SCG_FIRC_ASYNC_DIV2_CLK 13U
      30           0 : #define KINETIS_SCG_SPLL_ASYNC_DIV1_CLK 14U
      31           0 : #define KINETIS_SCG_SPLL_ASYNC_DIV2_CLK 15U
      32             : 
      33             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_ */