Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2017, NXP
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_
       9              : 
      10            0 : #define KINETIS_SIM_CORESYS_CLK         0
      11            0 : #define KINETIS_SIM_PLATFORM_CLK        1
      12            0 : #define KINETIS_SIM_BUS_CLK             2
      13            0 : #define KINETIS_SIM_FAST_PERIPHERAL_CLK 5
      14            0 : #define KINETIS_SIM_LPO_CLK             19
      15            0 : #define KINETIS_SIM_DMAMUX_CLK  KINETIS_SIM_BUS_CLK
      16            0 : #define KINETIS_SIM_DMA_CLK     KINETIS_SIM_CORESYS_CLK
      17            0 : #define KINETIS_SIM_SIM_SOPT7   7
      18            0 : #define KINETIS_SIM_OSCERCLK    8
      19            0 : #define KINETIS_SIM_MCGIRCLK    12
      20            0 : #define KINETIS_SIM_MCGPCLK     18
      21              : 
      22            0 : #define KINETIS_SIM_PLLFLLSEL_MCGFLLCLK 0
      23            0 : #define KINETIS_SIM_PLLFLLSEL_MCGPLLCLK 1
      24            0 : #define KINETIS_SIM_PLLFLLSEL_IRC48MHZ  3
      25              : 
      26            0 : #define KINETIS_SIM_ER32KSEL_OSC32KCLK  0
      27            0 : #define KINETIS_SIM_ER32KSEL_RTC        2
      28            0 : #define KINETIS_SIM_ER32KSEL_LPO1KHZ    3
      29              : 
      30            0 : #define KINETIS_SIM_ENET_CLK            4321
      31            0 : #define KINETIS_SIM_ENET_1588_CLK       4322
      32              : 
      33              : 
      34              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_ */