Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 IoT.bzh
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A7795_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A7795_H_
       9              : 
      10              : #include "renesas_cpg_mssr.h"
      11              : 
      12              : /* r8a7795 CPG Core Clocks */
      13            0 : #define R8A7795_CLK_Z                   0
      14            0 : #define R8A7795_CLK_Z2                  1
      15            0 : #define R8A7795_CLK_ZR                  2
      16            0 : #define R8A7795_CLK_ZG                  3
      17            0 : #define R8A7795_CLK_ZTR                 4
      18            0 : #define R8A7795_CLK_ZTRD2               5
      19            0 : #define R8A7795_CLK_ZT                  6
      20            0 : #define R8A7795_CLK_ZX                  7
      21            0 : #define R8A7795_CLK_S0D1                8
      22            0 : #define R8A7795_CLK_S0D4                9
      23            0 : #define R8A7795_CLK_S1D1                10
      24            0 : #define R8A7795_CLK_S1D2                11
      25            0 : #define R8A7795_CLK_S1D4                12
      26            0 : #define R8A7795_CLK_S2D1                13
      27            0 : #define R8A7795_CLK_S2D2                14
      28            0 : #define R8A7795_CLK_S2D4                15
      29            0 : #define R8A7795_CLK_S3D1                16
      30            0 : #define R8A7795_CLK_S3D2                17
      31            0 : #define R8A7795_CLK_S3D4                18  /* SCIF clock */
      32            0 : #define R8A7795_CLK_LB                  19
      33            0 : #define R8A7795_CLK_CL                  20
      34            0 : #define R8A7795_CLK_ZB3                 21
      35            0 : #define R8A7795_CLK_ZB3D2               22
      36            0 : #define R8A7795_CLK_CR                  23
      37            0 : #define R8A7795_CLK_CRD2                24
      38            0 : #define R8A7795_CLK_SD0H                25
      39            0 : #define R8A7795_CLK_SD0                 26
      40            0 : #define R8A7795_CLK_SD1H                27
      41            0 : #define R8A7795_CLK_SD1                 28
      42            0 : #define R8A7795_CLK_SD2H                29
      43            0 : #define R8A7795_CLK_SD2                 30
      44            0 : #define R8A7795_CLK_SD3H                31
      45            0 : #define R8A7795_CLK_SD3                 32
      46            0 : #define R8A7795_CLK_SSP2                33
      47            0 : #define R8A7795_CLK_SSP1                34
      48            0 : #define R8A7795_CLK_SSPRS               35
      49            0 : #define R8A7795_CLK_RPC                 36
      50            0 : #define R8A7795_CLK_RPCD2               37
      51            0 : #define R8A7795_CLK_MSO                 38
      52            0 : #define R8A7795_CLK_CANFD               39  /* CANFD clock */
      53            0 : #define R8A7795_CLK_HDMI                40
      54            0 : #define R8A7795_CLK_CSI0                41
      55              : /* CLK_CSIREF was removed */
      56            0 : #define R8A7795_CLK_CP                  43
      57            0 : #define R8A7795_CLK_CPEX                44
      58            0 : #define R8A7795_CLK_R                   45
      59            0 : #define R8A7795_CLK_OSC                 46
      60              : 
      61              : /* r8a7795 ES2.0 CPG Core Clocks */
      62            0 : #define R8A7795_CLK_S0D2                47
      63            0 : #define R8A7795_CLK_S0D3                48
      64            0 : #define R8A7795_CLK_S0D6                49
      65            0 : #define R8A7795_CLK_S0D8                50
      66            0 : #define R8A7795_CLK_S0D12               51
      67              : 
      68              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A7795_H_ */