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1 0 : /* 2 : * Copyright (c) 2023 IoT.bzh 3 : * 4 : * SPDX-License-Identifier: Apache-2.0 5 : */ 6 : 7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_ 8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_ 9 : 10 : #include "renesas_cpg_mssr.h" 11 : 12 : /* r8a779f0 CPG Core Clocks */ 13 0 : #define R8A779F0_CLK_Z0 0 14 0 : #define R8A779F0_CLK_Z1 1 15 0 : #define R8A779F0_CLK_ZR 2 16 0 : #define R8A779F0_CLK_ZX 3 17 0 : #define R8A779F0_CLK_ZS 4 18 0 : #define R8A779F0_CLK_ZT 5 19 0 : #define R8A779F0_CLK_ZTR 6 20 0 : #define R8A779F0_CLK_S0D2 7 21 0 : #define R8A779F0_CLK_S0D3 8 22 0 : #define R8A779F0_CLK_S0D4 9 23 0 : #define R8A779F0_CLK_S0D2_MM 10 24 0 : #define R8A779F0_CLK_S0D3_MM 11 25 0 : #define R8A779F0_CLK_S0D4_MM 12 26 0 : #define R8A779F0_CLK_S0D2_RT 13 27 0 : #define R8A779F0_CLK_S0D3_RT 14 28 0 : #define R8A779F0_CLK_S0D4_RT 15 29 0 : #define R8A779F0_CLK_S0D6_RT 16 30 0 : #define R8A779F0_CLK_S0D3_PER 17 31 0 : #define R8A779F0_CLK_S0D6_PER 18 32 0 : #define R8A779F0_CLK_S0D12_PER 19 33 0 : #define R8A779F0_CLK_S0D24_PER 20 34 0 : #define R8A779F0_CLK_S0D2_HSC 21 35 0 : #define R8A779F0_CLK_S0D3_HSC 22 36 0 : #define R8A779F0_CLK_S0D4_HSC 23 37 0 : #define R8A779F0_CLK_S0D6_HSC 24 38 0 : #define R8A779F0_CLK_S0D12_HSC 25 39 0 : #define R8A779F0_CLK_S0D2_CC 26 40 0 : #define R8A779F0_CLK_CL 27 41 0 : #define R8A779F0_CLK_CL16M 28 42 0 : #define R8A779F0_CLK_CL16M_MM 29 43 0 : #define R8A779F0_CLK_CL16M_RT 30 44 0 : #define R8A779F0_CLK_CL16M_PER 31 45 0 : #define R8A779F0_CLK_CL16M_HSC 32 46 0 : #define R8A779F0_CLK_ZB3 33 47 0 : #define R8A779F0_CLK_ZB3D2 34 48 0 : #define R8A779F0_CLK_ZB3D4 35 49 0 : #define R8A779F0_CLK_SD0H 36 50 0 : #define R8A779F0_CLK_SD0 37 51 0 : #define R8A779F0_CLK_RPC 38 52 0 : #define R8A779F0_CLK_RPCD2 39 53 0 : #define R8A779F0_CLK_MSO 40 54 0 : #define R8A779F0_CLK_POST 41 55 0 : #define R8A779F0_CLK_POST2 42 56 0 : #define R8A779F0_CLK_SASYNCRT 43 57 0 : #define R8A779F0_CLK_SASYNCPERD1 44 58 0 : #define R8A779F0_CLK_SASYNCPERD2 45 59 0 : #define R8A779F0_CLK_SASYNCPERD4 46 60 0 : #define R8A779F0_CLK_DBGSOC_HSC 47 61 0 : #define R8A779F0_CLK_RSW2 48 62 0 : #define R8A779F0_CLK_CPEX 49 63 0 : #define R8A779F0_CLK_CBFUSA 50 64 0 : #define R8A779F0_CLK_R 51 65 0 : #define R8A779F0_CLK_OSC 52 66 : 67 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_ */