LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/clock - rx_clock.h Coverage Total Hit
Test: new.info Lines: 0.0 % 69 0
Test Date: 2025-09-25 19:22:35

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2024 Renesas Electronics Corporation
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RX_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RX_H_
       9              : 
      10            0 : #define RX_CLOCKS_SOURCE_CLOCK_LOCO     0
      11            0 : #define RX_CLOCKS_SOURCE_CLOCK_HOCO     1
      12            0 : #define RX_CLOCKS_SOURCE_CLOCK_MAIN_OSC 2
      13            0 : #define RX_CLOCKS_SOURCE_CLOCK_SUBCLOCK 3
      14            0 : #define RX_CLOCKS_SOURCE_PLL            4
      15            0 : #define RX_CLOCKS_SOURCE_CLOCK_DISABLE  0xff
      16              : 
      17            0 : #define RX_IF_CLOCKS_SOURCE_CLOCK_HOCO 0
      18            0 : #define RX_IF_CLOCKS_SOURCE_CLOCK_LOCO 2
      19            0 : #define RX_IF_CLOCKS_SOURCE_PLL        5
      20            0 : #define RX_IF_CLOCKS_SOURCE_PLL2       6
      21              : 
      22            0 : #define RX_LPT_CLOCKS_SOURCE_CLOCK_SUBCLOCK       0
      23            0 : #define RX_LPT_CLOCKS_SOURCE_CLOCK_IWDT_LOW_SPEED 1
      24            0 : #define RX_LPT_CLOCKS_NON_USE                     2
      25            0 : #define RX_LPT_CLOCKS_SOURCE_CLOCK_LOCO           3
      26              : 
      27              : #ifdef CONFIG_SOC_SERIES_RX26T
      28              : #define RX_PLL_CLOCKS_SOURCE_CLOCK_MAIN_OSC 0
      29              : #define RX_PLL_CLOCKS_SOURCE_CLOCK_HOCO     1
      30              : #endif /* CONFIG_SOC_SERIES_RX26T */
      31              : 
      32            0 : #define RX_PLL_MUL_4   7
      33            0 : #define RX_PLL_MUL_4_5 8
      34            0 : #define RX_PLL_MUL_5   9
      35            0 : #define RX_PLL_MUL_5_5 10
      36            0 : #define RX_PLL_MUL_6   11
      37            0 : #define RX_PLL_MUL_6_5 12
      38            0 : #define RX_PLL_MUL_7   13
      39            0 : #define RX_PLL_MUL_7_5 14
      40            0 : #define RX_PLL_MUL_8   15
      41              : 
      42            0 : #define RX_PLL_MUL_10   19
      43            0 : #define RX_PLL_MUL_10_5 20
      44            0 : #define RX_PLL_MUL_11   21
      45            0 : #define RX_PLL_MUL_11_5 22
      46            0 : #define RX_PLL_MUL_12   23
      47            0 : #define RX_PLL_MUL_12_5 24
      48            0 : #define RX_PLL_MUL_13   25
      49            0 : #define RX_PLL_MUL_13_5 26
      50            0 : #define RX_PLL_MUL_14   27
      51            0 : #define RX_PLL_MUL_14_5 28
      52            0 : #define RX_PLL_MUL_15   29
      53            0 : #define RX_PLL_MUL_15_5 30
      54            0 : #define RX_PLL_MUL_16   31
      55            0 : #define RX_PLL_MUL_16_5 32
      56            0 : #define RX_PLL_MUL_17   33
      57            0 : #define RX_PLL_MUL_17_5 34
      58            0 : #define RX_PLL_MUL_18   35
      59            0 : #define RX_PLL_MUL_18_5 36
      60            0 : #define RX_PLL_MUL_19   37
      61            0 : #define RX_PLL_MUL_19_5 38
      62            0 : #define RX_PLL_MUL_20   39
      63            0 : #define RX_PLL_MUL_20_5 40
      64            0 : #define RX_PLL_MUL_21   41
      65            0 : #define RX_PLL_MUL_21_5 42
      66            0 : #define RX_PLL_MUL_22   43
      67            0 : #define RX_PLL_MUL_22_5 44
      68            0 : #define RX_PLL_MUL_23   45
      69            0 : #define RX_PLL_MUL_23_5 46
      70            0 : #define RX_PLL_MUL_24   47
      71            0 : #define RX_PLL_MUL_24_5 48
      72            0 : #define RX_PLL_MUL_25   49
      73            0 : #define RX_PLL_MUL_25_5 50
      74            0 : #define RX_PLL_MUL_26   51
      75            0 : #define RX_PLL_MUL_26_5 52
      76            0 : #define RX_PLL_MUL_27   53
      77            0 : #define RX_PLL_MUL_27_5 54
      78            0 : #define RX_PLL_MUL_28   55
      79            0 : #define RX_PLL_MUL_28_5 56
      80            0 : #define RX_PLL_MUL_29   57
      81            0 : #define RX_PLL_MUL_29_5 58
      82            0 : #define RX_PLL_MUL_30   59
      83              : 
      84            0 : #define MSTPA 0
      85            0 : #define MSTPB 1
      86            0 : #define MSTPC 2
      87            0 : #define MSTPD 3
      88              : 
      89              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RX_H_ */
        

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