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1 0 : /*
2 : * Copyright (c) 2024 Renesas Electronics Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RX_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RX_H_
9 :
10 0 : #define RX_CLOCKS_SOURCE_CLOCK_LOCO 0
11 0 : #define RX_CLOCKS_SOURCE_CLOCK_HOCO 1
12 0 : #define RX_CLOCKS_SOURCE_CLOCK_MAIN_OSC 2
13 0 : #define RX_CLOCKS_SOURCE_CLOCK_SUBCLOCK 3
14 0 : #define RX_CLOCKS_SOURCE_PLL 4
15 0 : #define RX_CLOCKS_SOURCE_CLOCK_DISABLE 0xff
16 :
17 0 : #define RX_IF_CLOCKS_SOURCE_CLOCK_HOCO 0
18 0 : #define RX_IF_CLOCKS_SOURCE_CLOCK_LOCO 2
19 0 : #define RX_IF_CLOCKS_SOURCE_PLL 5
20 0 : #define RX_IF_CLOCKS_SOURCE_PLL2 6
21 :
22 0 : #define RX_LPT_CLOCKS_SOURCE_CLOCK_SUBCLOCK 0
23 0 : #define RX_LPT_CLOCKS_SOURCE_CLOCK_IWDT_LOW_SPEED 1
24 0 : #define RX_LPT_CLOCKS_NON_USE 2
25 0 : #define RX_LPT_CLOCKS_SOURCE_CLOCK_LOCO 3
26 :
27 0 : #define RX_PLL_MUL_4 7
28 0 : #define RX_PLL_MUL_4_5 8
29 0 : #define RX_PLL_MUL_5 9
30 0 : #define RX_PLL_MUL_5_5 10
31 0 : #define RX_PLL_MUL_6 11
32 0 : #define RX_PLL_MUL_6_5 12
33 0 : #define RX_PLL_MUL_7 13
34 0 : #define RX_PLL_MUL_7_5 14
35 0 : #define RX_PLL_MUL_8 15
36 :
37 0 : #define MSTPA 0
38 0 : #define MSTPB 1
39 0 : #define MSTPC 2
40 0 : #define MSTPD 3
41 :
42 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RX_H_ */
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