Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2024 Silicon Laboratories Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_
       9              : 
      10              : /*
      11              :  * DT macros for clock branches.
      12              :  * Must stay in sync with the enum sl_clock_branch_t in the Silicon Labs HAL to be
      13              :  * interpreted correctly by the clock control driver.
      14              :  */
      15            0 : #define CLOCK_BRANCH_SYSCLK       0
      16            0 : #define CLOCK_BRANCH_HCLK         1
      17            0 : #define CLOCK_BRANCH_HCLKRADIO    2
      18            0 : #define CLOCK_BRANCH_PCLK         3
      19            0 : #define CLOCK_BRANCH_LSPCLK       4
      20            0 : #define CLOCK_BRANCH_TRACECLK     5
      21            0 : #define CLOCK_BRANCH_ADCCLK       6
      22            0 : #define CLOCK_BRANCH_EXPORTCLK    7
      23            0 : #define CLOCK_BRANCH_EM01GRPACLK  8
      24            0 : #define CLOCK_BRANCH_EM01GRPBCLK  9
      25            0 : #define CLOCK_BRANCH_EM01GRPCCLK  10
      26            0 : #define CLOCK_BRANCH_EM01GRPDCLK  11
      27            0 : #define CLOCK_BRANCH_EM23GRPACLK  12
      28            0 : #define CLOCK_BRANCH_EM4GRPACLK   13
      29            0 : #define CLOCK_BRANCH_QSPISYSCLK   14
      30            0 : #define CLOCK_BRANCH_IADCCLK      15
      31            0 : #define CLOCK_BRANCH_WDOG0CLK     16
      32            0 : #define CLOCK_BRANCH_WDOG1CLK     17
      33            0 : #define CLOCK_BRANCH_RTCCCLK      18
      34            0 : #define CLOCK_BRANCH_SYSRTCCLK    19
      35            0 : #define CLOCK_BRANCH_EUART0CLK    20
      36            0 : #define CLOCK_BRANCH_EUSART0CLK   21
      37            0 : #define CLOCK_BRANCH_EUSART1CLK   22
      38            0 : #define CLOCK_BRANCH_DPLLREFCLK   23
      39            0 : #define CLOCK_BRANCH_I2C0CLK      24
      40            0 : #define CLOCK_BRANCH_LCDCLK       25
      41            0 : #define CLOCK_BRANCH_PIXELRZCLK   26
      42            0 : #define CLOCK_BRANCH_PCNT0CLK     27
      43            0 : #define CLOCK_BRANCH_PRORTCCLK    28
      44            0 : #define CLOCK_BRANCH_SYSTICKCLK   29
      45            0 : #define CLOCK_BRANCH_LESENSEHFCLK 30
      46            0 : #define CLOCK_BRANCH_VDAC0CLK     31
      47            0 : #define CLOCK_BRANCH_VDAC1CLK     32
      48            0 : #define CLOCK_BRANCH_USB0CLK      33
      49            0 : #define CLOCK_BRANCH_FLPLLREFCLK  34
      50            0 : #define CLOCK_BRANCH_INVALID      35
      51              : 
      52            0 : #define CLOCK_BIT_MASK 0x03FUL
      53            0 : #define CLOCK_REG_MASK 0x1C0UL
      54              : 
      55              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ */