Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2024 Silicon Laboratories Inc.
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  *
       6             :  * This file was generated by the script gen_clock_control.py in the hal_silabs module.
       7             :  * Do not manually edit.
       8             :  */
       9             : 
      10             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_
      11             : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_
      12             : 
      13             : #include <zephyr/dt-bindings/dt-util.h>
      14             : #include "common-clock.h"
      15             : 
      16             : /*
      17             :  * DT macros for clock tree nodes.
      18             :  * Defined as:
      19             :  *  0..5 - Bit within CLKEN register
      20             :  *  6..8 - CLKEN register number
      21             :  * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be
      22             :  * interpreted correctly by the clock control driver.
      23             :  */
      24           0 : #define CLOCK_AUTO 0xFFFFFFFFUL
      25             : 
      26             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_ */