Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2024 Silicon Laboratories Inc.
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  *
       6             :  * This file was generated by the script gen_clock_control.py in the hal_silabs module.
       7             :  * Do not manually edit.
       8             :  */
       9             : 
      10             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_
      11             : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_
      12             : 
      13             : #include <zephyr/dt-bindings/dt-util.h>
      14             : #include "common-clock.h"
      15             : 
      16             : /*
      17             :  * DT macros for clock tree nodes.
      18             :  * Defined as:
      19             :  *  0..5 - Bit within CLKEN register
      20             :  *  6..8 - CLKEN register number
      21             :  * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be
      22             :  * interpreted correctly by the clock control driver.
      23             :  */
      24           0 : #define CLOCK_ACMP0         (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19))
      25           0 : #define CLOCK_AGC           (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
      26           0 : #define CLOCK_AMUXCP0       (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
      27           0 : #define CLOCK_BUFC          (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
      28           0 : #define CLOCK_BURAM         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
      29           0 : #define CLOCK_BURTC         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
      30           0 : #define CLOCK_CRYPTOACC     (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13))
      31           0 : #define CLOCK_DCDC          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
      32           0 : #define CLOCK_DPLL0         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
      33           0 : #define CLOCK_ETAMPDET      (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28))
      34           0 : #define CLOCK_EUSART0       (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20))
      35           0 : #define CLOCK_FRC           (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3))
      36           0 : #define CLOCK_FSRCO         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20))
      37           0 : #define CLOCK_GPCRC0        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3))
      38           0 : #define CLOCK_GPIO          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26))
      39           0 : #define CLOCK_HFRCO0        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18))
      40           0 : #define CLOCK_HFXO0         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19))
      41           0 : #define CLOCK_I2C0          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14))
      42           0 : #define CLOCK_I2C1          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15))
      43           0 : #define CLOCK_IADC0         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10))
      44           0 : #define CLOCK_ICACHE0       (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16))
      45           0 : #define CLOCK_IFADCDEBUG    (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12))
      46           0 : #define CLOCK_LDMA0         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0))
      47           0 : #define CLOCK_LDMAXBAR0     (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1))
      48           0 : #define CLOCK_LETIMER0      (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12))
      49           0 : #define CLOCK_LFRCO         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21))
      50           0 : #define CLOCK_LFXO          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22))
      51           0 : #define CLOCK_MODEM         (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1))
      52           0 : #define CLOCK_MSC           (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17))
      53           0 : #define CLOCK_PDM           (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25))
      54           0 : #define CLOCK_PRORTC        (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10))
      55           0 : #define CLOCK_PROTIMER      (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4))
      56           0 : #define CLOCK_PRS           (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27))
      57           0 : #define CLOCK_RAC           (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5))
      58           0 : #define CLOCK_RADIOAES      (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2))
      59           0 : #define CLOCK_RDMAILBOX0    (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8))
      60           0 : #define CLOCK_RDMAILBOX1    (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9))
      61           0 : #define CLOCK_RDSCRATCHPAD  (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7))
      62           0 : #define CLOCK_RFCRC         (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2))
      63           0 : #define CLOCK_RFSENSE       (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14))
      64           0 : #define CLOCK_RTCC          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30))
      65           0 : #define CLOCK_SMU           (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15))
      66           0 : #define CLOCK_SYNTH         (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6))
      67           0 : #define CLOCK_SYSCFG        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16))
      68           0 : #define CLOCK_TIMER0        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4))
      69           0 : #define CLOCK_TIMER1        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5))
      70           0 : #define CLOCK_TIMER2        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6))
      71           0 : #define CLOCK_TIMER3        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7))
      72           0 : #define CLOCK_TIMER4        (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18))
      73           0 : #define CLOCK_ULFRCO        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23))
      74           0 : #define CLOCK_USART0        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8))
      75           0 : #define CLOCK_USART1        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9))
      76           0 : #define CLOCK_WDOG0         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13))
      77             : 
      78             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_ */