Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2023 STMicroelectronics
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_
       8              : 
       9              : /** System clock */
      10            1 : #define STM32_SRC_SYSCLK        0x001
      11              : /** Fixed clocks  */
      12            1 : #define STM32_SRC_LSE           0x002
      13            0 : #define STM32_SRC_LSI           0x003
      14              : 
      15              : /** Dummy: Add a specifier when no selection is possible */
      16            1 : #define NO_SEL                  0xFF
      17              : 
      18            0 : #define STM32_CLOCK_DIV_SHIFT   12
      19              : 
      20              : /** Clock divider */
      21            1 : #define STM32_CLOCK_DIV(div)    (((div) - 1) << STM32_CLOCK_DIV_SHIFT)
      22              : 
      23              : /** Helper macros to pack RCC clock source selection register info in the DT */
      24            1 : #define STM32_DT_CLKSEL_REG_MASK        0xFFFFU
      25            0 : #define STM32_DT_CLKSEL_REG_SHIFT       0U
      26            0 : #define STM32_DT_CLKSEL_SHIFT_MASK      0x3FU
      27            0 : #define STM32_DT_CLKSEL_SHIFT_SHIFT     16U
      28            0 : #define STM32_DT_CLKSEL_MASK_MASK       0x1FU
      29            0 : #define STM32_DT_CLKSEL_MASK_SHIFT      22U
      30            0 : #define STM32_DT_CLKSEL_VAL_MASK        0x1FU
      31            0 : #define STM32_DT_CLKSEL_VAL_SHIFT       27U
      32              : 
      33              : /**
      34              :  * @brief Pack STM32 source clock selection RCC register bit fields for the DT
      35              :  *
      36              :  * @param val    Clock configuration field value
      37              :  * @param mask   Mask of register field in RCC register
      38              :  * @param shift  Position of field within RCC register (= field LSB's index)
      39              :  * @param reg    Offset to target clock configuration register in RCC
      40              :  *
      41              :  * @note 'reg' range:    0x0~0xFFFF   [ 00 : 15 ]
      42              :  * @note 'shift' range:  0~63         [ 16 : 21 ]
      43              :  * @note 'mask' range:   0x00~0x1F    [ 22 : 26 ]
      44              :  * @note 'val' range:    0x00~0x1F    [ 27 : 31 ]
      45              :  */
      46            1 : #define STM32_DT_CLOCK_SELECT(val, mask, shift, reg)                                    \
      47              :         ((((reg) & STM32_DT_CLKSEL_REG_MASK) << STM32_DT_CLKSEL_REG_SHIFT) |          \
      48              :          (((shift) & STM32_DT_CLKSEL_SHIFT_MASK) << STM32_DT_CLKSEL_SHIFT_SHIFT) |    \
      49              :          (((mask) & STM32_DT_CLKSEL_MASK_MASK) << STM32_DT_CLKSEL_MASK_SHIFT) |               \
      50              :          (((val) & STM32_DT_CLKSEL_VAL_MASK) << STM32_DT_CLKSEL_VAL_SHIFT))
      51              : 
      52              : /**
      53              :  * Pack RCC clock register offset and bit in two 32-bit values
      54              :  * as expected for the Device Tree `clocks` property on STM32.
      55              :  *
      56              :  * @param bus STM32 bus name (expands to STM32_CLOCK_BUS_{bus})
      57              :  * @param bit Clock bit
      58              :  */
      59            1 : #define STM32_CLOCK(bus, bit) (STM32_CLOCK_BUS_##bus) (1 << bit)
      60              : 
      61              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_ */