Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_
       8              : 
       9              : #include "stm32_common_clocks.h"
      10              : 
      11              : /** Bus clocks */
      12            1 : #define STM32_CLOCK_BUS_IOP     0x034
      13            0 : #define STM32_CLOCK_BUS_AHB1    0x038
      14            0 : #define STM32_CLOCK_BUS_APB1    0x03c
      15            0 : #define STM32_CLOCK_BUS_APB1_2  0x040
      16              : 
      17            0 : #define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_IOP
      18            0 : #define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB1_2
      19              : 
      20              : /** Domain clocks */
      21              : /* RM0490, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */
      22              : 
      23              : /** System clock */
      24              : /* defined in stm32_common_clocks.h */
      25              : /** Fixed clocks  */
      26              : /* Low speed clocks defined in stm32_common_clocks.h
      27              :  * STM32_SRC_HSI relates to HSI48 clock mentioned in RM0490 Reference Manual
      28              :  * STM32_SRC_HSI48 relates to HSIUSB48 mentioned in RM0490 Reference Manual
      29              :  */
      30            1 : #define STM32_SRC_HSI           (STM32_SRC_LSI + 1)
      31            0 : #define STM32_SRC_HSI48         (STM32_SRC_HSI + 1)
      32            0 : #define STM32_SRC_HSE           (STM32_SRC_HSI48 + 1)
      33              : /** Peripheral bus clock */
      34            1 : #define STM32_SRC_PCLK          (STM32_SRC_HSE + 1)
      35            0 : #define STM32_SRC_TIMPCLK1      (STM32_SRC_PCLK + 1)
      36              : 
      37              : /** @brief RCC_CCIPR register offset */
      38            1 : #define CCIPR_REG               0x54
      39            0 : #define CCIPR2_REG              0x58
      40              : 
      41              : /** @brief RCC_CSR1 register offset */
      42            1 : #define CSR1_REG                0x5C
      43              : 
      44              : /** @brief RCC_CFGRx register offset */
      45            1 : #define CFGR1_REG               0x08
      46              : 
      47              : /** @brief Device domain clocks selection helpers */
      48              : /** CCIPR devices */
      49            1 : #define USART1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
      50            0 : #define FDCAN_SEL(val)          STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
      51            0 : #define I2C1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
      52            0 : #define I2C2_I2S1_SEL(val)      STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
      53            0 : #define ADC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
      54              : /** CCIPR2 devices */
      55            1 : #define USB_SEL(val)            STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR2_REG)
      56              : /** CSR1 devices */
      57            1 : #define RTC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 8, CSR1_REG)
      58              : 
      59              : /** CFGR1 devices */
      60            1 : #define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0xf, 24, CFGR1_REG)
      61            0 : #define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0xf, 28, CFGR1_REG)
      62            0 : #define MCO2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0xf, 16, CFGR1_REG)
      63            0 : #define MCO2_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0xf, 20, CFGR1_REG)
      64              : 
      65              : /* MCO prescaler : division factor */
      66            0 : #define MCO_PRE_DIV_1   0
      67            0 : #define MCO_PRE_DIV_2   1
      68            0 : #define MCO_PRE_DIV_4   2
      69            0 : #define MCO_PRE_DIV_8   3
      70            0 : #define MCO_PRE_DIV_16  4
      71            0 : #define MCO_PRE_DIV_32  5
      72            0 : #define MCO_PRE_DIV_64  6
      73            0 : #define MCO_PRE_DIV_128 7
      74              : 
      75              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */