Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 Linaro Limited
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
       8              : 
       9              : #include "stm32_common_clocks.h"
      10              : 
      11              : /** Domain clocks */
      12              : 
      13              : /** Bus clocks */
      14            1 : #define STM32_CLOCK_BUS_AHB1    0x014
      15            0 : #define STM32_CLOCK_BUS_APB2    0x018
      16            0 : #define STM32_CLOCK_BUS_APB1    0x01c
      17              : 
      18            0 : #define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_AHB1
      19            0 : #define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB1
      20              : 
      21              : /** System clock */
      22              : /* defined in stm32_common_clocks.h */
      23              : 
      24              : /** Fixed clocks  */
      25              : /* Low speed clocks defined in stm32_common_clocks.h */
      26            1 : #define STM32_SRC_HSI           (STM32_SRC_LSI + 1)
      27            0 : #define STM32_SRC_HSE           (STM32_SRC_HSI + 1)
      28            0 : #define STM32_SRC_EXT_HSE       (STM32_SRC_HSE + 1)
      29            0 : #define STM32_SRC_PLLCLK        (STM32_SRC_EXT_HSE + 1)
      30            0 : #define STM32_SRC_TIMPCLK1      (STM32_SRC_PLLCLK + 1)
      31            0 : #define STM32_SRC_TIMPCLK2      (STM32_SRC_TIMPCLK1 + 1)
      32              : 
      33              : /** @brief RCC_CFGRx register offset */
      34            1 : #define CFGR1_REG               0x04
      35            0 : #define CFGR2_REG               0x2C
      36              : 
      37              : /** @brief RCC_BDCR register offset */
      38            1 : #define BDCR_REG                0x20
      39              : 
      40              : /** @brief Device domain clocks selection helpers */
      41              : /** CFGR2 devices */
      42            1 : #define I2S2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 1, 17, CFGR2_REG)
      43            0 : #define I2S3_SEL(val)           STM32_DT_CLOCK_SELECT((val), 1, 18, CFGR2_REG)
      44              : /** BDCR devices */
      45            1 : #define RTC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
      46              : 
      47              : /** CFGR1 devices */
      48            1 : #define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG)
      49              : /* No MCO prescaler support on STM32F1 series. */
      50              : 
      51              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */