LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/clock - stm32f410_clock.h Hit Total Coverage
Test: new.info Lines: 3 14 21.4 %
Date: 2024-12-22 00:14:23

          Line data    Source code
       1           0 : /*
       2             :  * Copyright (c) 2023 Linaro Limited
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_
       8             : 
       9             : /** @brief RCC_DCKCFGR register offset */
      10           1 : #define DCKCFGR_REG             0x8C
      11           0 : #define DCKCFGR2_REG            0x94
      12             : 
      13             : /** @brief Device domain clocks selection helpers */
      14             : /** DCKCFGR devices */
      15           1 : #define CKDFSDM2A_SEL(val)      STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG)
      16           0 : #define CKDFSDM1A_SEL(val)      STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG)
      17           0 : #define SAI1A_SEL(val)          STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG)
      18           0 : #define SAI1B_SEL(val)          STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG)
      19           0 : #define I2S1_SEL(val)           STM32_DOMAIN_CLOCK(val, 3, 25, DCKCFGR_REG)
      20           0 : #define I2S2_SEL(val)           STM32_DOMAIN_CLOCK(val, 3, 27, DCKCFGR_REG)
      21           0 : #define CKDFSDM_SEL(val)        STM32_DOMAIN_CLOCK(val, 1, 31, DCKCFGR_REG)
      22             : 
      23             : /** DCKCFGR2 devices */
      24           1 : #define I2CFMP1_SEL(val)        STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)
      25           0 : #define CK48M_SEL(val)          STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)
      26           0 : #define SDIO_SEL(val)           STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)
      27           0 : #define LPTIM1_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 30, DCKCFGR2_REG)
      28             : 
      29             : /* F4 generic I2S_SEL is not compatible with F410 devices */
      30             : #ifdef I2S_SEL
      31             : #undef I2S_SEL
      32             : #endif
      33             : 
      34             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ */

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