Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2022 Linaro Limited
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_
       8             : 
       9             : #include "stm32_common_clocks.h"
      10             : 
      11             : /** Domain clocks */
      12             : 
      13             : /** Bus clocks */
      14           1 : #define STM32_CLOCK_BUS_AHB1 0x030
      15           0 : #define STM32_CLOCK_BUS_AHB2 0x034
      16           0 : #define STM32_CLOCK_BUS_AHB3 0x038
      17           0 : #define STM32_CLOCK_BUS_APB1 0x040
      18           0 : #define STM32_CLOCK_BUS_APB2 0x044
      19           0 : #define STM32_CLOCK_BUS_APB3 0x0A8
      20             : 
      21           0 : #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
      22           0 : #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
      23             : 
      24             : /** Domain clocks */
      25             : /* RM0386, 0390, 0402, 0430 § Dedicated Clock configuration register (RCC_DCKCFGRx) */
      26             : 
      27             : /** System clock */
      28             : /* defined in stm32_common_clocks.h */
      29             : /** Fixed clocks */
      30             : /* Low speed clocks defined in stm32_common_clocks.h */
      31           1 : #define STM32_SRC_HSI           (STM32_SRC_LSI + 1)
      32           0 : #define STM32_SRC_HSE           (STM32_SRC_HSI + 1)
      33             : /** PLL clock outputs */
      34           1 : #define STM32_SRC_PLL_P         (STM32_SRC_HSE + 1)
      35           0 : #define STM32_SRC_PLL_Q         (STM32_SRC_PLL_P + 1)
      36           0 : #define STM32_SRC_PLL_R         (STM32_SRC_PLL_Q + 1)
      37             : /** I2S sources */
      38           1 : #define STM32_SRC_PLLI2S_Q      (STM32_SRC_PLL_R + 1)
      39           0 : #define STM32_SRC_PLLI2S_R      (STM32_SRC_PLLI2S_Q + 1)
      40             : /* CLK48MHz sources */
      41           0 : #define STM32_SRC_CK48          (STM32_SRC_PLLI2S_R + 1)
      42             : 
      43             : /* I2S_CKIN not supported yet */
      44             : /* #define STM32_SRC_I2S_CKIN   TBD */
      45             : 
      46           0 : #define STM32_CLOCK_REG_MASK    0xFFU
      47           0 : #define STM32_CLOCK_REG_SHIFT   0U
      48           0 : #define STM32_CLOCK_SHIFT_MASK  0x1FU
      49           0 : #define STM32_CLOCK_SHIFT_SHIFT 8U
      50           0 : #define STM32_CLOCK_MASK_MASK   0x7U
      51           0 : #define STM32_CLOCK_MASK_SHIFT  13U
      52           0 : #define STM32_CLOCK_VAL_MASK    0x7U
      53           0 : #define STM32_CLOCK_VAL_SHIFT   16U
      54             : 
      55             : /**
      56             :  * @brief STM32 clock configuration bit field.
      57             :  *
      58             :  * - reg   (1/2/3)         [ 0 : 7 ]
      59             :  * - shift (0..31)         [ 8 : 12 ]
      60             :  * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
      61             :  * - val   (0..7)          [ 16 : 18 ]
      62             :  *
      63             :  * @param reg RCC_CFGRx register offset
      64             :  * @param shift Position within RCC_CFGRx.
      65             :  * @param mask Mask for the RCC_CFGRx field.
      66             :  * @param val Clock value (0, 1, ... 7).
      67             :  */
      68           1 : #define STM32_DOMAIN_CLOCK(val, mask, shift, reg)                                                  \
      69             :         ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |                               \
      70             :          (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |                         \
      71             :          (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |                            \
      72             :          (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
      73             : 
      74             : /** @brief RCC_CFGRx register offset */
      75           1 : #define CFGR_REG 0x08
      76             : /** @brief RCC_BDCR register offset */
      77           1 : #define BDCR_REG 0x70
      78             : 
      79             : /** @brief Device domain clocks selection helpers */
      80             : /** CFGR devices */
      81           1 : #define I2S_SEL(val)  STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
      82           0 : #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)
      83           0 : #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
      84           0 : #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
      85           0 : #define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
      86             : /** BDCR devices */
      87           1 : #define RTC_SEL(val)  STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
      88             : 
      89             : /* MCO prescaler : division factor */
      90           0 : #define MCO_PRE_DIV_1 0
      91           0 : #define MCO_PRE_DIV_2 4
      92           0 : #define MCO_PRE_DIV_3 5
      93           0 : #define MCO_PRE_DIV_4 6
      94           0 : #define MCO_PRE_DIV_5 7
      95             : 
      96             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ */