Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 Linaro Limited
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_
       8              : 
       9              : #include "stm32_common_clocks.h"
      10              : 
      11              : /** Domain clocks */
      12              : 
      13              : /** Bus clocks */
      14            1 : #define STM32_CLOCK_BUS_AHB1 0x030
      15            0 : #define STM32_CLOCK_BUS_AHB2 0x034
      16            0 : #define STM32_CLOCK_BUS_AHB3 0x038
      17            0 : #define STM32_CLOCK_BUS_APB1 0x040
      18            0 : #define STM32_CLOCK_BUS_APB2 0x044
      19            0 : #define STM32_CLOCK_BUS_APB3 0x0A8
      20              : 
      21            0 : #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
      22            0 : #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
      23              : 
      24              : /** Domain clocks */
      25              : /* RM0386, 0390, 0402, 0430 § Dedicated Clock configuration register (RCC_DCKCFGRx) */
      26              : 
      27              : /** System clock */
      28              : /* defined in stm32_common_clocks.h */
      29              : /** Fixed clocks */
      30              : /* Low speed clocks defined in stm32_common_clocks.h */
      31            1 : #define STM32_SRC_HSI           (STM32_SRC_LSI + 1)
      32            0 : #define STM32_SRC_HSE           (STM32_SRC_HSI + 1)
      33              : /** PLL clock outputs */
      34            1 : #define STM32_SRC_PLL_P         (STM32_SRC_HSE + 1)
      35            0 : #define STM32_SRC_PLL_Q         (STM32_SRC_PLL_P + 1)
      36            0 : #define STM32_SRC_PLL_R         (STM32_SRC_PLL_Q + 1)
      37              : /** I2S sources */
      38            1 : #define STM32_SRC_PLLI2S_Q      (STM32_SRC_PLL_R + 1)
      39            0 : #define STM32_SRC_PLLI2S_R      (STM32_SRC_PLLI2S_Q + 1)
      40              : /* CLK48MHz sources */
      41            0 : #define STM32_SRC_CK48          (STM32_SRC_PLLI2S_R + 1)
      42              : /** Bus clock */
      43            1 : #define STM32_SRC_TIMPCLK1      (STM32_SRC_CK48 + 1)
      44            0 : #define STM32_SRC_TIMPCLK2      (STM32_SRC_TIMPCLK1 + 1)
      45              : 
      46              : /* PLLSAI clocks */
      47            0 : #define STM32_SRC_PLLSAI_P      (STM32_SRC_TIMPCLK2 + 1)
      48            0 : #define STM32_SRC_PLLSAI_Q      (STM32_SRC_PLLSAI_P + 1)
      49            0 : #define STM32_SRC_PLLSAI_DIVQ   (STM32_SRC_PLLSAI_Q + 1)
      50            0 : #define STM32_SRC_PLLSAI_R      (STM32_SRC_PLLSAI_DIVQ + 1)
      51            0 : #define STM32_SRC_PLLSAI_DIVR   (STM32_SRC_PLLSAI_R + 1)
      52              : 
      53              : /* I2S_CKIN not supported yet */
      54              : /* #define STM32_SRC_I2S_CKIN   TBD */
      55              : 
      56              : /** @brief RCC_CFGRx register offset */
      57            1 : #define CFGR_REG 0x08
      58              : /** @brief RCC_BDCR register offset */
      59            1 : #define BDCR_REG 0x70
      60              : 
      61              : /** @brief Device domain clocks selection helpers */
      62              : /** CFGR devices */
      63            1 : #define I2S_SEL(val)  STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG)
      64            0 : #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG)
      65            0 : #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG)
      66            0 : #define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG)
      67            0 : #define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG)
      68              : /** BDCR devices */
      69            1 : #define RTC_SEL(val)  STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
      70              : 
      71              : /* MCO prescaler : division factor */
      72            0 : #define MCO_PRE_DIV_1 0
      73            0 : #define MCO_PRE_DIV_2 4
      74            0 : #define MCO_PRE_DIV_3 5
      75            0 : #define MCO_PRE_DIV_4 6
      76            0 : #define MCO_PRE_DIV_5 7
      77              : 
      78              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ */