LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/clock - stm32g4_clock.h Coverage Total Hit
Test: new.info Lines: 22.0 % 41 9
Test Date: 2025-09-05 20:47:19

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2022 Linaro Limited
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_
       8              : 
       9              : #include "stm32_common_clocks.h"
      10              : 
      11              : /** Bus clocks */
      12            1 : #define STM32_CLOCK_BUS_AHB1    0x048
      13            0 : #define STM32_CLOCK_BUS_AHB2    0x04c
      14            0 : #define STM32_CLOCK_BUS_AHB3    0x050
      15            0 : #define STM32_CLOCK_BUS_APB1    0x058
      16            0 : #define STM32_CLOCK_BUS_APB1_2  0x05c
      17            0 : #define STM32_CLOCK_BUS_APB2    0x060
      18              : 
      19            0 : #define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_AHB1
      20            0 : #define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB2
      21              : 
      22              : /** Domain clocks */
      23              : /* RM0440, ยง Clock configuration register (RCC_CCIPRx) */
      24              : 
      25              : /** System clock */
      26              : /* defined in stm32_common_clocks.h */
      27              : 
      28              : /** Fixed clocks  */
      29              : /* Low speed clocks defined in stm32_common_clocks.h */
      30            1 : #define STM32_SRC_HSI           (STM32_SRC_LSI + 1)
      31            0 : #define STM32_SRC_HSI48         (STM32_SRC_HSI + 1)
      32            0 : #define STM32_SRC_HSE           (STM32_SRC_HSI48 + 1)
      33            0 : #define STM32_SRC_MSI           (STM32_SRC_HSE + 1)
      34              : /** Bus clock */
      35            1 : #define STM32_SRC_PCLK          (STM32_SRC_MSI + 1)
      36            0 : #define STM32_SRC_TIMPCLK1      (STM32_SRC_PCLK + 1)
      37            0 : #define STM32_SRC_TIMPCLK2      (STM32_SRC_TIMPCLK1 + 1)
      38              : /** PLL clock outputs */
      39            1 : #define STM32_SRC_PLL_P         (STM32_SRC_TIMPCLK2 + 1)
      40            0 : #define STM32_SRC_PLL_Q         (STM32_SRC_PLL_P + 1)
      41            0 : #define STM32_SRC_PLL_R         (STM32_SRC_PLL_Q + 1)
      42              : /* TODO: PLLSAI clocks */
      43              : 
      44              : /** @brief RCC_CCIPR register offset */
      45            1 : #define CCIPR_REG               0x88
      46            0 : #define CCIPR2_REG              0x9C
      47              : 
      48              : /** @brief RCC_BDCR register offset */
      49            1 : #define BDCR_REG                0x90
      50              : 
      51              : /** @brief Device domain clocks selection helpers */
      52              : /** CCIPR devices */
      53            1 : #define USART1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
      54            0 : #define USART2_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
      55            0 : #define USART3_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG)
      56            0 : #define USART4_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG)
      57            0 : #define USART5_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
      58            0 : #define LPUART1_SEL(val)        STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
      59            0 : #define I2C1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
      60            0 : #define I2C2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
      61            0 : #define I2C3_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
      62            0 : #define LPTIM1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
      63            0 : #define SAI1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
      64            0 : #define I2S23_SEL(val)          STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
      65            0 : #define FDCAN_SEL(val)          STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR_REG)
      66            0 : #define CLK48_SEL(val)          STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
      67            0 : #define ADC12_SEL(val)          STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
      68            0 : #define ADC34_SEL(val)          STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
      69              : /** CCIPR2 devices */
      70            1 : #define I2C4_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
      71            0 : #define QSPI_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG)
      72              : /** BDCR devices */
      73            1 : #define RTC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
      74              : 
      75              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_ */
        

Generated by: LCOV version 2.0-1