Line data Source code
1 0 : /*
2 : * Copyright (c) 2022 Linaro Limited
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_
7 : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_
8 :
9 : #include "stm32_common_clocks.h"
10 :
11 : /** Bus clocks */
12 1 : #define STM32_CLOCK_BUS_AHB1 0x048
13 0 : #define STM32_CLOCK_BUS_AHB2 0x04c
14 0 : #define STM32_CLOCK_BUS_AHB3 0x050
15 0 : #define STM32_CLOCK_BUS_APB1 0x058
16 0 : #define STM32_CLOCK_BUS_APB1_2 0x05c
17 0 : #define STM32_CLOCK_BUS_APB2 0x060
18 :
19 0 : #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
20 0 : #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
21 :
22 : /** Domain clocks */
23 : /* RM0440, ยง Clock configuration register (RCC_CCIPRx) */
24 :
25 : /** System clock */
26 : /* defined in stm32_common_clocks.h */
27 :
28 : /** Fixed clocks */
29 : /* Low speed clocks defined in stm32_common_clocks.h */
30 1 : #define STM32_SRC_HSI (STM32_SRC_LSI + 1)
31 0 : #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
32 0 : #define STM32_SRC_HSE (STM32_SRC_HSI48 + 1)
33 0 : #define STM32_SRC_MSI (STM32_SRC_HSE + 1)
34 : /** Bus clock */
35 1 : #define STM32_SRC_PCLK (STM32_SRC_MSI + 1)
36 : /** PLL clock outputs */
37 1 : #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1)
38 0 : #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
39 0 : #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
40 : /* TODO: PLLSAI clocks */
41 :
42 0 : #define STM32_CLOCK_REG_MASK 0xFFU
43 0 : #define STM32_CLOCK_REG_SHIFT 0U
44 0 : #define STM32_CLOCK_SHIFT_MASK 0x1FU
45 0 : #define STM32_CLOCK_SHIFT_SHIFT 8U
46 0 : #define STM32_CLOCK_MASK_MASK 0x7U
47 0 : #define STM32_CLOCK_MASK_SHIFT 13U
48 0 : #define STM32_CLOCK_VAL_MASK 0x7U
49 0 : #define STM32_CLOCK_VAL_SHIFT 16U
50 :
51 : /**
52 : * @brief STM32 clock configuration bit field.
53 : *
54 : * - reg (1/2/3) [ 0 : 7 ]
55 : * - shift (0..31) [ 8 : 12 ]
56 : * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
57 : * - val (0..7) [ 16 : 18 ]
58 : *
59 : * @param reg RCC_CCIPRx register offset
60 : * @param shift Position within RCC_CCIPRx.
61 : * @param mask Mask for the RCC_CCIPRx field.
62 : * @param val Clock value (0, 1, ... 7).
63 : */
64 1 : #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
65 : ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
66 : (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
67 : (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
68 : (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
69 :
70 : /** @brief RCC_CCIPR register offset */
71 1 : #define CCIPR_REG 0x88
72 0 : #define CCIPR2_REG 0x9C
73 :
74 : /** @brief RCC_BDCR register offset */
75 1 : #define BDCR_REG 0x90
76 :
77 : /** @brief Device domain clocks selection helpers */
78 : /** CCIPR devices */
79 1 : #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
80 0 : #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
81 0 : #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
82 0 : #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG)
83 0 : #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
84 0 : #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
85 0 : #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
86 0 : #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
87 0 : #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
88 0 : #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
89 0 : #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
90 0 : #define I2S23_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
91 0 : #define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR_REG)
92 0 : #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
93 0 : #define ADC12_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
94 0 : #define ADC34_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
95 : /** CCIPR2 devices */
96 1 : #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG)
97 0 : #define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG)
98 : /** BDCR devices */
99 1 : #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
100 :
101 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_ */
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