Line data Source code
1 0 : /*
2 : * Copyright (c) 2022 Linaro Limited
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
7 : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
8 :
9 : #include "stm32_common_clocks.h"
10 :
11 : /** Domain clocks */
12 :
13 : /* RM0468, Table 56 Kernel clock dictribution summary */
14 :
15 : /** System clock */
16 : /* defined in stm32_common_clocks.h */
17 :
18 : /** Fixed clocks */
19 : /* Low speed clocks defined in stm32_common_clocks.h */
20 1 : #define STM32_SRC_HSE (STM32_SRC_LSI + 1)
21 0 : #define STM32_SRC_HSI48 (STM32_SRC_HSE + 1)
22 0 : #define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1) /* HSI + HSIKERON */
23 0 : #define STM32_SRC_CSI_KER (STM32_SRC_HSI_KER + 1) /* CSI + CSIKERON */
24 : /** PLL outputs */
25 1 : #define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1)
26 0 : #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
27 0 : #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
28 0 : #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
29 0 : #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
30 0 : #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
31 0 : #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
32 0 : #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
33 0 : #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
34 : /** Clock muxes */
35 1 : #define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1)
36 : /** Others: Not yet supported */
37 : /* #define STM32_SRC_I2SCKIN TBD */
38 : /* #define STM32_SRC_SPDIFRX TBD */
39 :
40 :
41 : /** Bus clocks */
42 1 : #define STM32_CLOCK_BUS_AHB3 0x0D4
43 0 : #define STM32_CLOCK_BUS_AHB1 0x0D8
44 0 : #define STM32_CLOCK_BUS_AHB2 0x0DC
45 0 : #define STM32_CLOCK_BUS_AHB4 0x0E0
46 0 : #define STM32_CLOCK_BUS_APB3 0x0E4
47 0 : #define STM32_CLOCK_BUS_APB1 0x0E8
48 0 : #define STM32_CLOCK_BUS_APB1_2 0x0EC
49 0 : #define STM32_CLOCK_BUS_APB2 0x0F0
50 0 : #define STM32_CLOCK_BUS_APB4 0x0F4
51 : /** Alias D1/2/3 domains clocks */ /* TBD: To remove ? */
52 1 : #define STM32_SRC_PCLK1 STM32_CLOCK_BUS_APB1
53 0 : #define STM32_SRC_PCLK2 STM32_CLOCK_BUS_APB2
54 0 : #define STM32_SRC_HCLK3 STM32_CLOCK_BUS_AHB3
55 0 : #define STM32_SRC_PCLK3 STM32_CLOCK_BUS_APB3
56 0 : #define STM32_SRC_PCLK4 STM32_CLOCK_BUS_APB4
57 :
58 0 : #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3
59 0 : #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4
60 :
61 0 : #define STM32_CLOCK_REG_MASK 0xFFU
62 0 : #define STM32_CLOCK_REG_SHIFT 0U
63 0 : #define STM32_CLOCK_SHIFT_MASK 0x1FU
64 0 : #define STM32_CLOCK_SHIFT_SHIFT 8U
65 0 : #define STM32_CLOCK_MASK_MASK 0x7U
66 0 : #define STM32_CLOCK_MASK_SHIFT 13U
67 0 : #define STM32_CLOCK_VAL_MASK 0x7U
68 0 : #define STM32_CLOCK_VAL_SHIFT 16U
69 :
70 : /**
71 : * @brief STM32H7 clock configuration bit field.
72 : *
73 : * - reg (0/1) [ 0 : 7 ]
74 : * - shift (0..31) [ 8 : 12 ]
75 : * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
76 : * - val (0..3) [ 16 : 18 ]
77 : *
78 : * @param reg RCC_DxCCIP register offset
79 : * @param shift Position within RCC_DxCCIP.
80 : * @param mask Mask for the RCC_DxCCIP field.
81 : * @param val Clock value (0, 1, 2 or 3).
82 : */
83 1 : #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
84 : ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
85 : (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
86 : (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
87 : (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
88 :
89 : /** @brief RCC_DxCCIP register offset (RM0399.pdf) */
90 1 : #define D1CCIPR_REG 0x4C
91 0 : #define D2CCIP1R_REG 0x50
92 0 : #define D2CCIP2R_REG 0x54
93 0 : #define D3CCIPR_REG 0x58
94 :
95 : /** @brief RCC_BDCR register offset */
96 1 : #define BDCR_REG 0x70
97 :
98 : /** @brief RCC_CFGRx register offset */
99 1 : #define CFGR_REG 0x10
100 :
101 : /** @brief Device domain clocks selection helpers (RM0399.pdf) */
102 : /** D1CCIPR devices */
103 1 : #define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)
104 0 : #define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
105 0 : #define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, D1CCIPR_REG)
106 0 : #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, D1CCIPR_REG)
107 0 : #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG)
108 : /* Device domain clocks selection helpers (RM0468.pdf) */
109 0 : #define OSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
110 : /** D2CCIP1R devices */
111 1 : #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP1R_REG)
112 0 : #define SAI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, D2CCIP1R_REG)
113 0 : #define SPI123_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, D2CCIP1R_REG)
114 0 : #define SPI45_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIP1R_REG)
115 0 : #define SPDIF_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP1R_REG)
116 0 : #define DFSDM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, D2CCIP1R_REG)
117 0 : #define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D2CCIP1R_REG)
118 0 : #define SWP_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, D2CCIP1R_REG)
119 : /** D2CCIP2R devices */
120 1 : #define USART2345678_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP2R_REG)
121 0 : #define USART16_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, D2CCIP2R_REG)
122 0 : #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIP2R_REG)
123 0 : #define I2C123_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIP2R_REG)
124 0 : #define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP2R_REG)
125 0 : #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIP2R_REG)
126 0 : #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D2CCIP2R_REG)
127 : /** D3CCIPR devices */
128 1 : #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)
129 0 : #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D3CCIPR_REG)
130 0 : #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 10, D3CCIPR_REG)
131 0 : #define LPTIM345_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 13, D3CCIPR_REG)
132 0 : #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, D3CCIPR_REG)
133 0 : #define SAI4A_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, D3CCIPR_REG)
134 0 : #define SAI4B_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, D3CCIPR_REG)
135 0 : #define SPI6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D3CCIPR_REG)
136 : /** BDCR devices */
137 1 : #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
138 : /** CFGR devices */
139 1 : #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 22, CFGR_REG)
140 0 : #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 18, CFGR_REG)
141 0 : #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0xF, 29, CFGR_REG)
142 0 : #define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 25, CFGR_REG)
143 :
144 : /* MCO prescaler : division factor */
145 0 : #define MCO_PRE_DIV_1 1
146 0 : #define MCO_PRE_DIV_2 2
147 0 : #define MCO_PRE_DIV_3 3
148 0 : #define MCO_PRE_DIV_4 4
149 0 : #define MCO_PRE_DIV_5 5
150 0 : #define MCO_PRE_DIV_6 6
151 0 : #define MCO_PRE_DIV_7 7
152 0 : #define MCO_PRE_DIV_8 8
153 0 : #define MCO_PRE_DIV_9 9
154 0 : #define MCO_PRE_DIV_10 10
155 0 : #define MCO_PRE_DIV_11 11
156 0 : #define MCO_PRE_DIV_12 12
157 0 : #define MCO_PRE_DIV_13 13
158 0 : #define MCO_PRE_DIV_14 14
159 0 : #define MCO_PRE_DIV_15 15
160 :
161 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */
|
