Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 Linaro Limited
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
       8              : 
       9              : #include "stm32_common_clocks.h"
      10              : 
      11              : /** Bus gatting clocks */
      12            1 : #define STM32_CLOCK_BUS_IOP     0x02c
      13            0 : #define STM32_CLOCK_BUS_AHB1    0x030
      14            0 : #define STM32_CLOCK_BUS_APB2    0x034
      15            0 : #define STM32_CLOCK_BUS_APB1    0x038
      16              : 
      17            0 : #define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_IOP
      18            0 : #define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB1
      19              : 
      20              : /** Domain clocks */
      21              : /* RM0367, §7.3.20 Clock configuration register (RCC_CCIPR) */
      22              : 
      23              : /** System clock */
      24              : /* defined in stm32_common_clocks.h */
      25              : 
      26              : /** Fixed clocks  */
      27              : /* Low speed clocks defined in stm32_common_clocks.h */
      28            1 : #define STM32_SRC_HSE           (STM32_SRC_LSI + 1)
      29            0 : #define STM32_SRC_HSI           (STM32_SRC_HSE + 1)
      30            0 : #define STM32_SRC_HSI48         (STM32_SRC_HSI + 1)
      31              : /** Bus clock */
      32            1 : #define STM32_SRC_PCLK          (STM32_SRC_HSI48 + 1)
      33            0 : #define STM32_SRC_TIMPCLK1      (STM32_SRC_PCLK + 1)
      34            0 : #define STM32_SRC_TIMPCLK2      (STM32_SRC_TIMPCLK1 + 1)
      35              : 
      36              : /** @brief RCC_CCIPR register offset */
      37            1 : #define CCIPR_REG               0x4C
      38              : 
      39              : /** @brief RCC_CSR register offset */
      40            1 : #define CSR_REG         0x50
      41              : 
      42              : /** @brief Device domain clocks selection helpers */
      43              : /** CCIPR devices */
      44            1 : #define USART1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
      45            0 : #define USART2_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
      46            0 : #define LPUART1_SEL(val)        STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
      47            0 : #define I2C1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
      48            0 : #define I2C3_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
      49            0 : #define LPTIM1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
      50            0 : #define HSI48_SEL(val)          STM32_DT_CLOCK_SELECT((val), 1, 26, CCIPR_REG)
      51              : /** CSR devices */
      52            1 : #define RTC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 16, CSR_REG)
      53              : 
      54              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */