Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2024 STMicroelectronics
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U0_CLOCK_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U0_CLOCK_H_
       8              : 
       9              : #include "stm32_common_clocks.h"
      10              : 
      11              : /** Bus gatting clocks */
      12            1 : #define STM32_CLOCK_BUS_AHB1    0x48
      13            0 : #define STM32_CLOCK_BUS_IOP     0x4C
      14            0 : #define STM32_CLOCK_BUS_APB1    0x58
      15            0 : #define STM32_CLOCK_BUS_APB1_2  0x60
      16              : 
      17            0 : #define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_AHB1
      18            0 : #define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB1_2
      19              : 
      20              : /** Domain clocks */
      21              : /* RM0503, clock configuration register (RCC_CCIPR) */
      22              : 
      23              : /** System clock */
      24              : /* defined in stm32_common_clocks.h */
      25              : 
      26              : /** Fixed clocks  */
      27              : /* Low speed clocks defined in stm32_common_clocks.h */
      28            1 : #define STM32_SRC_HSI           (STM32_SRC_LSI + 1)
      29            0 : #define STM32_SRC_HSI48         (STM32_SRC_HSI + 1)
      30            0 : #define STM32_SRC_MSI           (STM32_SRC_HSI48 + 1)
      31            0 : #define STM32_SRC_HSE           (STM32_SRC_MSI + 1)
      32              : /** Peripheral bus clock */
      33            1 : #define STM32_SRC_PCLK          (STM32_SRC_HSE + 1)
      34              : /** PLL clock outputs */
      35            1 : #define STM32_SRC_PLL_P         (STM32_SRC_PCLK + 1)
      36            0 : #define STM32_SRC_PLL_Q         (STM32_SRC_PLL_P + 1)
      37            0 : #define STM32_SRC_PLL_R         (STM32_SRC_PLL_Q + 1)
      38              : 
      39              : /** @brief RCC_CCIPR register offset */
      40            1 : #define CCIPR_REG               0x88
      41              : 
      42              : /** @brief RCC_BDCR register offset */
      43            1 : #define BDCR_REG                0x90
      44              : 
      45              : /** @brief Device domain clocks selection helpers */
      46              : /** CCIPR devices */
      47            1 : #define USART1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
      48            0 : #define USART2_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
      49            0 : #define LPUART3_SEL(val)        STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG)
      50            0 : #define LPUART2_SEL(val)        STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
      51            0 : #define LPUART1_SEL(val)        STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
      52            0 : #define I2C1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
      53            0 : #define I2C3_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
      54            0 : #define LPTIM1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
      55            0 : #define LPTIM2_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
      56            0 : #define LPTIM3_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
      57            0 : #define TIM1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG)
      58            0 : #define TIM15_SEL(val)          STM32_DT_CLOCK_SELECT((val), 1, 25, CCIPR_REG)
      59            0 : #define CLK48_SEL(val)          STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
      60            0 : #define ADC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
      61              : /** BDCR devices */
      62            1 : #define RTC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
      63              : 
      64              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U0_CLOCK_H_ */