Line data Source code
1 0 : /*
2 : * Copyright (c) 2022 Linaro Limited
3 : * Copyright (c) 2023 STMicroelectronics
4 : *
5 : * SPDX-License-Identifier: Apache-2.0
6 : */
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
9 :
10 : #include "stm32_common_clocks.h"
11 :
12 : /** Domain clocks */
13 :
14 : /* RM0468, Table 56 Kernel clock distribution summary */
15 :
16 : /** System clock */
17 : /* defined in stm32_common_clocks.h */
18 : /** Fixed clocks */
19 1 : #define STM32_SRC_HSE (STM32_SRC_LSI + 1)
20 0 : #define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
21 0 : #define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1)
22 0 : #define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1)
23 0 : #define STM32_SRC_MSIK (STM32_SRC_MSIS + 1)
24 : /** Bus clock */
25 1 : #define STM32_SRC_HCLK (STM32_SRC_MSIK + 1)
26 0 : #define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1)
27 0 : #define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
28 0 : #define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1)
29 : /** PLL outputs */
30 1 : #define STM32_SRC_PLL1_P (STM32_SRC_PCLK3 + 1)
31 0 : #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
32 0 : #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
33 0 : #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
34 0 : #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
35 0 : #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
36 0 : #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
37 0 : #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
38 0 : #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
39 : /** Clock muxes */
40 : /* #define STM32_SRC_ICLK TBD */
41 :
42 : /** Bus clocks */
43 1 : #define STM32_CLOCK_BUS_AHB1 0x088
44 0 : #define STM32_CLOCK_BUS_AHB2 0x08C
45 0 : #define STM32_CLOCK_BUS_AHB2_2 0x090
46 0 : #define STM32_CLOCK_BUS_AHB3 0x094
47 0 : #define STM32_CLOCK_BUS_APB1 0x09C
48 0 : #define STM32_CLOCK_BUS_APB1_2 0x0A0
49 0 : #define STM32_CLOCK_BUS_APB2 0x0A4
50 0 : #define STM32_CLOCK_BUS_APB3 0x0A8
51 :
52 0 : #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
53 0 : #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
54 :
55 0 : #define STM32_CLOCK_REG_MASK 0xFFU
56 0 : #define STM32_CLOCK_REG_SHIFT 0U
57 0 : #define STM32_CLOCK_SHIFT_MASK 0x1FU
58 0 : #define STM32_CLOCK_SHIFT_SHIFT 8U
59 0 : #define STM32_CLOCK_MASK_MASK 0x7U
60 0 : #define STM32_CLOCK_MASK_SHIFT 13U
61 0 : #define STM32_CLOCK_VAL_MASK 0x7U
62 0 : #define STM32_CLOCK_VAL_SHIFT 16U
63 :
64 : /**
65 : * @brief STM32U5 clock configuration bit field.
66 : *
67 : * - reg (1/2/3) [ 0 : 7 ]
68 : * - shift (0..31) [ 8 : 12 ]
69 : * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
70 : * - val (0..7) [ 16 : 18 ]
71 : *
72 : * @param reg RCC_CCIPRx register offset
73 : * @param shift Position within RCC_CCIPRx.
74 : * @param mask Mask for the RCC_CCIPRx field.
75 : * @param val Clock value (0, 1, ... 7).
76 : */
77 1 : #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
78 : ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
79 : (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
80 : (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
81 : (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
82 :
83 : /** @brief RCC_CCIPRx register offset (RM0456.pdf) */
84 1 : #define CCIPR1_REG 0xE0
85 0 : #define CCIPR2_REG 0xE4
86 0 : #define CCIPR3_REG 0xE8
87 :
88 : /** @brief RCC_BDCR register offset */
89 1 : #define BDCR_REG 0xF0
90 :
91 : /** @brief RCC_CFGRx register offset */
92 1 : #define CFGR1_REG 0x1C
93 :
94 : /** @brief Device domain clocks selection helpers */
95 : /** CCIPR1 devices */
96 1 : #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG)
97 0 : #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG)
98 0 : #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR1_REG)
99 0 : #define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR1_REG)
100 0 : #define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR1_REG)
101 0 : #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG)
102 0 : #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR1_REG)
103 0 : #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR1_REG)
104 0 : #define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR1_REG)
105 0 : #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG)
106 0 : #define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG)
107 0 : #define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG)
108 0 : #define FDCAN1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR1_REG)
109 0 : #define ICKLK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR1_REG)
110 0 : #define TIMIC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 29, CCIPR1_REG)
111 : /** CCIPR2 devices */
112 1 : #define MDF1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR2_REG)
113 0 : #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 5, CCIPR2_REG)
114 0 : #define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG)
115 0 : #define SAE_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 11, CCIPR2_REG)
116 0 : #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)
117 0 : #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, CCIPR2_REG)
118 0 : #define DSIHOST_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, CCIPR2_REG)
119 0 : #define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, CCIPR2_REG)
120 0 : #define LTDC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 18, CCIPR2_REG)
121 0 : #define OCTOSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG)
122 0 : #define HSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR2_REG)
123 0 : #define I2C5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR2_REG)
124 0 : #define I2C6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR2_REG)
125 0 : #define OTGHS_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG)
126 : /** CCIPR3 devices */
127 1 : #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG)
128 0 : #define SPI3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG)
129 0 : #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR3_REG)
130 0 : #define LPTIM34_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR3_REG)
131 0 : #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR3_REG)
132 0 : #define ADCDAC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG)
133 0 : #define DAC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, CCIPR3_REG)
134 0 : #define ADF1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR3_REG)
135 : /** BDCR devices */
136 1 : #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
137 :
138 : /** CFGR1 devices */
139 1 : #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)
140 0 : #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
141 :
142 : /* MCO prescaler : division factor */
143 0 : #define MCO_PRE_DIV_1 0
144 0 : #define MCO_PRE_DIV_2 1
145 0 : #define MCO_PRE_DIV_4 2
146 0 : #define MCO_PRE_DIV_8 3
147 0 : #define MCO_PRE_DIV_16 4
148 :
149 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */
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