Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2024 STMicroelectronics
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
       8              : 
       9              : /** Define system & low-speed clocks */
      10              : #include "stm32_common_clocks.h"
      11              : 
      12              : /** Other fixed clocks.
      13              :  * - CLKSLOWMUX: used to query slow clock tree frequency
      14              :  * - CLK16MHZ: secondary clock for LPUART, SPI3/I2S and BLE
      15              :  * - CLK32MHZ: secondary clock for SPI3/I2S and BLE
      16              :  */
      17            1 : #define STM32_SRC_CLKSLOWMUX            (STM32_SRC_LSI + 1)
      18            0 : #define STM32_SRC_CLK16MHZ              (STM32_SRC_CLKSLOWMUX + 1)
      19            0 : #define STM32_SRC_CLK32MHZ              (STM32_SRC_CLK16MHZ + 1)
      20              : 
      21              : /** Bus clocks */
      22            1 : #define STM32_CLOCK_BUS_AHB0    0x50
      23            0 : #define STM32_CLOCK_BUS_APB0    0x54
      24            0 : #define STM32_CLOCK_BUS_APB1    0x58
      25            0 : #define STM32_CLOCK_BUS_APB2    0x60
      26              : 
      27            0 : #define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_AHB0
      28            0 : #define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB2
      29              : 
      30              : /** @brief RCC_CFGR register offset */
      31            1 : #define CFGR_REG        0x08
      32              : 
      33              : /** @brief RCC_APB2ENR register offset */
      34            1 : #define APB2ENR_REG     0x60
      35              : 
      36              : /** @brief Device clk sources selection helpers */
      37              : 
      38              : /* WB05/WB09 only */
      39            1 : #define LPUART1_SEL(val)        STM32_DT_CLOCK_SELECT((val), 1, 13, CFGR_REG)
      40              : /* WB06/WB07 only */
      41            0 : #define SPI2_I2S2_SEL(val)      STM32_DT_CLOCK_SELECT((val), 1, 22, CFGR_REG)
      42              : /* `mask` is only 0x1 for WB06/WB07, but a single definition with mask=0x3 is acceptable */
      43            0 : #define SPI3_I2S3_SEL(val)      STM32_DT_CLOCK_SELECT((val), 3, 22, CFGR_REG)
      44              : 
      45              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ */