Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2023 STMicroelectronics
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_
       8              : 
       9              : #include "stm32_common_clocks.h"
      10              : 
      11              : /** Peripheral clock sources */
      12              : 
      13              : /* RM0493, Figure 34, clock tree */
      14              : /* RM0515, Figure 36, clock tree */
      15              : 
      16              : /** System clock */
      17              : /* defined in stm32_common_clocks.h */
      18              : /** Fixed clocks  */
      19              : /* Low speed clocks defined in stm32_common_clocks.h */
      20            1 : #define STM32_SRC_HSE           (STM32_SRC_LSI + 1)
      21            0 : #define STM32_SRC_HSI16         (STM32_SRC_HSE + 1)
      22              : /** Bus clock */
      23            1 : #define STM32_SRC_HCLK1         (STM32_SRC_HSI16 + 1)
      24            0 : #define STM32_SRC_HCLK5         (STM32_SRC_HCLK1 + 1)
      25            0 : #define STM32_SRC_PCLK1         (STM32_SRC_HCLK5 + 1)
      26            0 : #define STM32_SRC_PCLK2         (STM32_SRC_PCLK1 + 1)
      27            0 : #define STM32_SRC_PCLK7         (STM32_SRC_PCLK2 + 1)
      28            0 : #define STM32_SRC_TIMPCLK1      (STM32_SRC_PCLK7 + 1)
      29            0 : #define STM32_SRC_TIMPCLK2      (STM32_SRC_TIMPCLK1 + 1)
      30              : /** PLL outputs */
      31            1 : #define STM32_SRC_PLL1_P        (STM32_SRC_TIMPCLK2 + 1)
      32            0 : #define STM32_SRC_PLL1_Q        (STM32_SRC_PLL1_P + 1)
      33            0 : #define STM32_SRC_PLL1_R        (STM32_SRC_PLL1_Q + 1)
      34              : 
      35            0 : #define STM32_SRC_CLOCK_MIN     STM32_SRC_PLL1_P
      36            0 : #define STM32_SRC_CLOCK_MAX     STM32_SRC_SYSCLK
      37              : 
      38              : /** Bus clocks (Register address offsets) */
      39            1 : #define STM32_CLOCK_BUS_AHB1    0x088
      40            0 : #define STM32_CLOCK_BUS_AHB2    0x08C
      41            0 : #define STM32_CLOCK_BUS_AHB4    0x094
      42            0 : #define STM32_CLOCK_BUS_AHB5    0x098
      43            0 : #define STM32_CLOCK_BUS_APB1    0x09C
      44            0 : #define STM32_CLOCK_BUS_APB1_2  0x0A0
      45            0 : #define STM32_CLOCK_BUS_APB2    0x0A4
      46            0 : #define STM32_CLOCK_BUS_APB7    0x0A8
      47              : 
      48            0 : #define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_AHB1
      49            0 : #define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB7
      50              : 
      51              : /** @brief RCC_CCIPRx register offset (RM0493.pdf) */
      52            1 : #define CCIPR1_REG              0xE0
      53            0 : #define CCIPR2_REG              0xE4
      54            0 : #define CCIPR3_REG              0xE8
      55              : /** @brief RCC_BCDR1 register offset (RM0493.pdf) */
      56            1 : #define BCDR1_REG               0xF0
      57              : 
      58              : /** @brief Device clk sources selection helpers */
      59              : /** CCIPR1 devices */
      60            1 : #define USART1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG)
      61            0 : #define USART2_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG)
      62            0 : #define USART3_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR1_REG)
      63            0 : #define I2C1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG)
      64            0 : #define I2C2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR1_REG)
      65            0 : #define I2C4_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR1_REG)
      66            0 : #define SPI2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR1_REG)
      67            0 : #define LPTIM2_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG)
      68            0 : #define SPI1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG)
      69            0 : #define SYSTICK_SEL(val)        STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG)
      70            0 : #define TIMIC_SEL(val)          STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG)
      71              : /** CCIPR2 devices */
      72            1 : #define RNG_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
      73              : /** CCIPR3 devices */
      74            1 : #define LPUART1_SEL(val)        STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
      75            0 : #define SPI3_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG)
      76            0 : #define I2C3_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR3_REG)
      77            0 : #define LPTIM1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG)
      78            0 : #define ADC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG)
      79              : /** BCDR1 devices */
      80            1 : #define RTC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 8, BCDR1_REG)
      81              : /** @brief RCC_CFGRx register offset */
      82            1 : #define CFGR1_REG               0x1C
      83              : /** CFGR1 devices */
      84            1 : #define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
      85            0 : #define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
      86              : 
      87              : /* MCO prescaler : division factor */
      88            0 : #define MCO_PRE_DIV_1 0
      89            0 : #define MCO_PRE_DIV_2 1
      90            0 : #define MCO_PRE_DIV_4 2
      91            0 : #define MCO_PRE_DIV_8 3
      92            0 : #define MCO_PRE_DIV_16 4
      93              : 
      94              : /* MCO clock output */
      95            0 : #define MCO_SEL_SYSCLKPRE 1
      96            0 : #define MCO_SEL_HSI16 3
      97            0 : #define MCO_SEL_HSE32 4
      98            0 : #define MCO_SEL_PLL1RCLK 5
      99            0 : #define MCO_SEL_LSI 6
     100            0 : #define MCO_SEL_LSE 7
     101            0 : #define MCO_SEL_PLL1PCLK 8
     102            0 : #define MCO_SEL_PLL1QCLK 9
     103            0 : #define MCO_SEL_HCLK5 10
     104              : 
     105              : 
     106              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ */