Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 Linaro Limited
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_
       8              : 
       9              : #include "stm32_common_clocks.h"
      10              : 
      11              : /** Bus clocks */
      12            1 : #define STM32_CLOCK_BUS_AHB1    0x048
      13            0 : #define STM32_CLOCK_BUS_AHB2    0x04c
      14            0 : #define STM32_CLOCK_BUS_AHB3    0x050
      15            0 : #define STM32_CLOCK_BUS_APB0    0x054
      16            0 : #define STM32_CLOCK_BUS_APB1    0x058
      17            0 : #define STM32_CLOCK_BUS_APB1_2  0x05c
      18            0 : #define STM32_CLOCK_BUS_APB2    0x060
      19            0 : #define STM32_CLOCK_BUS_APB3    0x064
      20              : 
      21            0 : #define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_AHB1
      22            0 : #define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB3
      23              : 
      24              : /** Domain clocks */
      25              : /* RM0461, §6.4.29 Clock configuration register (RCC_CFGR3) */
      26              : 
      27              : 
      28              : /** System clock */
      29              : /* defined in stm32_common_clocks.h */
      30              : /** Fixed clocks  */
      31              : /* Low speed clocks defined in stm32_common_clocks.h */
      32            1 : #define STM32_SRC_HSI           (STM32_SRC_LSI + 1)
      33            0 : #define STM32_SRC_MSI           (STM32_SRC_HSI + 1)
      34              : /* #define STM32_SRC_HSI48      TBD */
      35              : /** Bus clock */
      36            1 : #define STM32_SRC_PCLK          (STM32_SRC_MSI + 1)
      37            0 : #define STM32_SRC_TIMPCLK1      (STM32_SRC_PCLK + 1)
      38            0 : #define STM32_SRC_TIMPCLK2      (STM32_SRC_TIMPCLK1 + 1)
      39              : /** PLL clock outputs */
      40            1 : #define STM32_SRC_PLL_P         (STM32_SRC_TIMPCLK2 + 1)
      41            0 : #define STM32_SRC_PLL_Q         (STM32_SRC_PLL_P + 1)
      42            0 : #define STM32_SRC_PLL_R         (STM32_SRC_PLL_Q + 1)
      43              : 
      44              : /** @brief RCC_CCIPR register offset */
      45            1 : #define CCIPR_REG               0x88
      46              : 
      47              : /** @brief RCC_BDCR register offset */
      48            1 : #define BDCR_REG                0x90
      49              : 
      50              : /** @brief RCC_CFGRx register offset */
      51            1 : #define CFGR1_REG        0x08
      52              : 
      53              : /** @brief Device domain clocks selection helpers */
      54              : /** CCIPR devices */
      55            1 : #define USART1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
      56            0 : #define USART2_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
      57            0 : #define SPI2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
      58            0 : #define LPUART1_SEL(val)        STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
      59            0 : #define I2C1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
      60            0 : #define I2C2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
      61            0 : #define I2C3_SEL(val)           STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
      62            0 : #define LPTIM1_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
      63            0 : #define LPTIM2_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
      64            0 : #define LPTIM3_SEL(val)         STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
      65            0 : #define ADC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
      66            0 : #define RNG_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
      67              : /** BDCR devices */
      68            1 : #define RTC_SEL(val)            STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
      69              : /** CFGR1 devices */
      70            1 : #define MCO1_SEL(val)       STM32_DT_CLOCK_SELECT(val, 0xF, 24, CFGR1_REG)
      71            0 : #define MCO1_PRE(val)       STM32_DT_CLOCK_SELECT(val, 0x7, 28, CFGR1_REG)
      72              : 
      73              : /* MCO prescaler : division factor */
      74            0 : #define MCO_PRE_DIV_1  0
      75            0 : #define MCO_PRE_DIV_2  1
      76            0 : #define MCO_PRE_DIV_4  2
      77            0 : #define MCO_PRE_DIV_8  3
      78            0 : #define MCO_PRE_DIV_16 4
      79              : 
      80              : /* MCO clock output */
      81            0 : #define MCO_SEL_NOCLK     0
      82            0 : #define MCO_SEL_SYSCLKPRE 1
      83            0 : #define MCO_SEL_MSI       2
      84            0 : #define MCO_SEL_HSI16     3
      85            0 : #define MCO_SEL_HSE32     4
      86            0 : #define MCO_SEL_PLL1RCLK  5
      87            0 : #define MCO_SEL_LSI       6
      88            0 : #define MCO_SEL_LSE       8
      89            0 : #define MCO_SEL_PLL1PCLK  13
      90            0 : #define MCO_SEL_PLL1QCLK  14
      91              : 
      92              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_ */