Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2022 Linaro Limited
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_
       8             : 
       9             : #include "stm32_common_clocks.h"
      10             : 
      11             : /** Bus clocks */
      12           1 : #define STM32_CLOCK_BUS_AHB1    0x048
      13           0 : #define STM32_CLOCK_BUS_AHB2    0x04c
      14           0 : #define STM32_CLOCK_BUS_AHB3    0x050
      15           0 : #define STM32_CLOCK_BUS_APB1    0x058
      16           0 : #define STM32_CLOCK_BUS_APB1_2  0x05c
      17           0 : #define STM32_CLOCK_BUS_APB2    0x060
      18           0 : #define STM32_CLOCK_BUS_APB3    0x064
      19             : 
      20           0 : #define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_AHB1
      21           0 : #define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB3
      22             : 
      23             : /** Domain clocks */
      24             : /* RM0461, §6.4.29 Clock configuration register (RCC_CFGR3) */
      25             : 
      26             : 
      27             : /** System clock */
      28             : /* defined in stm32_common_clocks.h */
      29             : /** Fixed clocks  */
      30             : /* Low speed clocks defined in stm32_common_clocks.h */
      31           1 : #define STM32_SRC_HSI           (STM32_SRC_LSI + 1)
      32           0 : #define STM32_SRC_MSI           (STM32_SRC_HSI + 1)
      33             : /* #define STM32_SRC_HSI48      TBD */
      34             : /** Bus clock */
      35           1 : #define STM32_SRC_PCLK          (STM32_SRC_MSI + 1)
      36             : /** PLL clock outputs */
      37           1 : #define STM32_SRC_PLL_P         (STM32_SRC_PCLK + 1)
      38           0 : #define STM32_SRC_PLL_Q         (STM32_SRC_PLL_P + 1)
      39           0 : #define STM32_SRC_PLL_R         (STM32_SRC_PLL_Q + 1)
      40             : 
      41           0 : #define STM32_CLOCK_REG_MASK    0xFFU
      42           0 : #define STM32_CLOCK_REG_SHIFT   0U
      43           0 : #define STM32_CLOCK_SHIFT_MASK  0x1FU
      44           0 : #define STM32_CLOCK_SHIFT_SHIFT 8U
      45           0 : #define STM32_CLOCK_MASK_MASK   0x7U
      46           0 : #define STM32_CLOCK_MASK_SHIFT  13U
      47           0 : #define STM32_CLOCK_VAL_MASK    0x7U
      48           0 : #define STM32_CLOCK_VAL_SHIFT   16U
      49             : 
      50             : /**
      51             :  * @brief STM32 clock configuration bit field.
      52             :  *
      53             :  * - reg   (1/2/3)         [ 0 : 7 ]
      54             :  * - shift (0..31)         [ 8 : 12 ]
      55             :  * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
      56             :  * - val   (0..7)          [ 16 : 18 ]
      57             :  *
      58             :  * @param reg RCC_CCIPRx register offset
      59             :  * @param shift Position within RCC_CCIPRx.
      60             :  * @param mask Mask for the RCC_CCIPRx field.
      61             :  * @param val Clock value (0, 1, ... 7).
      62             :  */
      63           1 : #define STM32_DOMAIN_CLOCK(val, mask, shift, reg)                                       \
      64             :         ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |          \
      65             :          (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |    \
      66             :          (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |               \
      67             :          (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
      68             : 
      69             : /** @brief RCC_CCIPR register offset */
      70           1 : #define CCIPR_REG               0x88
      71             : 
      72             : /** @brief RCC_BDCR register offset */
      73           1 : #define BDCR_REG                0x90
      74             : 
      75             : /** @brief Device domain clocks selection helpers */
      76             : /** CCIPR devices */
      77           1 : #define USART1_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
      78           0 : #define USART2_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
      79           0 : #define SPI2_SEL(val)           STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
      80           0 : #define LPUART1_SEL(val)        STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
      81           0 : #define I2C1_SEL(val)           STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
      82           0 : #define I2C2_SEL(val)           STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
      83           0 : #define I2C3_SEL(val)           STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
      84           0 : #define LPTIM1_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
      85           0 : #define LPTIM2_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
      86           0 : #define LPTIM3_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
      87           0 : #define ADC_SEL(val)            STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
      88           0 : #define RNG_SEL(val)            STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
      89             : /** BDCR devices */
      90           1 : #define RTC_SEL(val)            STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
      91             : 
      92             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_ */