Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2025 Silicon Laboratories Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  *
       6              :  * This file was generated by the script gen_vdac.py in the hal_silabs module.
       7              :  * Do not manually edit.
       8              :  */
       9              : 
      10              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DAC_SILABS_VDAC_H_
      11              : #define ZEPHYR_INCLUDE_DT_BINDINGS_DAC_SILABS_VDAC_H_
      12              : 
      13            0 : #define VDAC_OUTPUT_AUX     0x0
      14            0 : #define VDAC_OUTPUT_PA0     0x10
      15            0 : #define VDAC_OUTPUT_PA1     0x11
      16            0 : #define VDAC_OUTPUT_PA2     0x12
      17            0 : #define VDAC_OUTPUT_PA3     0x13
      18            0 : #define VDAC_OUTPUT_PA4     0x14
      19            0 : #define VDAC_OUTPUT_PA5     0x15
      20            0 : #define VDAC_OUTPUT_PA6     0x16
      21            0 : #define VDAC_OUTPUT_PA7     0x17
      22            0 : #define VDAC_OUTPUT_PA8     0x18
      23            0 : #define VDAC_OUTPUT_PA9     0x19
      24            0 : #define VDAC_OUTPUT_PA10    0x1a
      25            0 : #define VDAC_OUTPUT_PA11    0x1b
      26            0 : #define VDAC_OUTPUT_PA12    0x1c
      27            0 : #define VDAC_OUTPUT_PA13    0x1d
      28            0 : #define VDAC_OUTPUT_PA14    0x1e
      29            0 : #define VDAC_OUTPUT_PA15    0x1f
      30            0 : #define VDAC_OUTPUT_PB0     0x20
      31            0 : #define VDAC_OUTPUT_PB1     0x21
      32            0 : #define VDAC_OUTPUT_PB2     0x22
      33            0 : #define VDAC_OUTPUT_PB3     0x23
      34            0 : #define VDAC_OUTPUT_PB4     0x24
      35            0 : #define VDAC_OUTPUT_PB5     0x25
      36            0 : #define VDAC_OUTPUT_PB6     0x26
      37            0 : #define VDAC_OUTPUT_PB7     0x27
      38            0 : #define VDAC_OUTPUT_PB8     0x28
      39            0 : #define VDAC_OUTPUT_PB9     0x29
      40            0 : #define VDAC_OUTPUT_PB10    0x2a
      41            0 : #define VDAC_OUTPUT_PB11    0x2b
      42            0 : #define VDAC_OUTPUT_PB12    0x2c
      43            0 : #define VDAC_OUTPUT_PB13    0x2d
      44            0 : #define VDAC_OUTPUT_PB14    0x2e
      45            0 : #define VDAC_OUTPUT_PB15    0x2f
      46            0 : #define VDAC_OUTPUT_PC0     0x30
      47            0 : #define VDAC_OUTPUT_PC1     0x31
      48            0 : #define VDAC_OUTPUT_PC2     0x32
      49            0 : #define VDAC_OUTPUT_PC3     0x33
      50            0 : #define VDAC_OUTPUT_PC4     0x34
      51            0 : #define VDAC_OUTPUT_PC5     0x35
      52            0 : #define VDAC_OUTPUT_PC6     0x36
      53            0 : #define VDAC_OUTPUT_PC7     0x37
      54            0 : #define VDAC_OUTPUT_PC8     0x38
      55            0 : #define VDAC_OUTPUT_PC9     0x39
      56            0 : #define VDAC_OUTPUT_PC10    0x3a
      57            0 : #define VDAC_OUTPUT_PC11    0x3b
      58            0 : #define VDAC_OUTPUT_PC12    0x3c
      59            0 : #define VDAC_OUTPUT_PC13    0x3d
      60            0 : #define VDAC_OUTPUT_PC14    0x3e
      61            0 : #define VDAC_OUTPUT_PC15    0x3f
      62            0 : #define VDAC_OUTPUT_PD0     0x40
      63            0 : #define VDAC_OUTPUT_PD1     0x41
      64            0 : #define VDAC_OUTPUT_PD2     0x42
      65            0 : #define VDAC_OUTPUT_PD3     0x43
      66            0 : #define VDAC_OUTPUT_PD4     0x44
      67            0 : #define VDAC_OUTPUT_PD5     0x45
      68            0 : #define VDAC_OUTPUT_PD6     0x46
      69            0 : #define VDAC_OUTPUT_PD7     0x47
      70            0 : #define VDAC_OUTPUT_PD8     0x48
      71            0 : #define VDAC_OUTPUT_PD9     0x49
      72            0 : #define VDAC_OUTPUT_PD10    0x4a
      73            0 : #define VDAC_OUTPUT_PD11    0x4b
      74            0 : #define VDAC_OUTPUT_PD12    0x4c
      75            0 : #define VDAC_OUTPUT_PD13    0x4d
      76            0 : #define VDAC_OUTPUT_PD14    0x4e
      77            0 : #define VDAC_OUTPUT_PD15    0x4f
      78              : 
      79              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DAC_SILABS_VDAC_H_ */