Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2025 Paul Wedeck
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_
       8              : 
       9            0 : #define CH32V003_ADC1_DMA 0
      10              : 
      11            0 : #define CH32V003_SPI1_RX_DMA 1
      12            0 : #define CH32V003_SPI1_TX_DMA 2
      13              : 
      14            0 : #define CH32V003_USART1_RX_DMA 4
      15            0 : #define CH32V003_USART1_TX_DMA 3
      16              : 
      17            0 : #define CH32V003_I2C1_RX_DMA 6
      18            0 : #define CH32V003_I2C1_TX_DMA 5
      19              : 
      20            0 : #define CH32V003_TIM1_CH1_DMA 1
      21            0 : #define CH32V003_TIM1_CH2_DMA 2
      22            0 : #define CH32V003_TIM1_CH3_DMA 5
      23            0 : #define CH32V003_TIM1_CH4_DMA 3
      24            0 : #define CH32V003_TIM1_TRIG 3
      25            0 : #define CH32V003_TIM1_COM 3
      26            0 : #define CH32V003_TIM1_UP 4
      27              : 
      28            0 : #define CH32V003_TIM2_CH1_DMA 4
      29            0 : #define CH32V003_TIM2_CH2_DMA 6
      30            0 : #define CH32V003_TIM2_CH3_DMA 0
      31            0 : #define CH32V003_TIM2_CH4_DMA 6
      32            0 : #define CH32V003_TIM2_UP 1
      33              : 
      34              : #endif /*ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_*/