Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_GD32_DMA_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_GD32_DMA_H_
       9              : 
      10              : /* macros for channel-cfg */
      11              : 
      12              : /* direction defined on bits 6-7 */
      13            0 : #define GD32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6)
      14            0 : #define GD32_DMA_MEMORY_TO_MEMORY      GD32_DMA_CH_CFG_DIRECTION(0)
      15            0 : #define GD32_DMA_MEMORY_TO_PERIPH      GD32_DMA_CH_CFG_DIRECTION(1)
      16            0 : #define GD32_DMA_PERIPH_TO_MEMORY      GD32_DMA_CH_CFG_DIRECTION(2)
      17              : 
      18              : /* periph increase defined on bit 9 as true/false */
      19            0 : #define GD32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9)
      20            0 : #define GD32_DMA_NO_PERIPH_ADDR_INC          GD32_DMA_CH_CFG_PERIPH_ADDR_INC(0)
      21            0 : #define GD32_DMA_PERIPH_ADDR_INC             GD32_DMA_CH_CFG_PERIPH_ADDR_INC(1)
      22              : 
      23              : /* memory increase defined on bit 10 as true/false */
      24            0 : #define GD32_DMA_CH_CFG_MEMORY_ADDR_INC(val) ((val & 0x1) << 10)
      25            0 : #define GD32_DMA_NO_MEMORY_ADDR_INC          GD32_DMA_CH_CFG_MEMORY_ADDR_INC(0)
      26            0 : #define GD32_DMA_MEMORY_ADDR_INC             GD32_DMA_CH_CFG_MEMORY_ADDR_INC(1)
      27              : 
      28              : /* periph data size defined on bits 11-12 */
      29            0 : #define GD32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11)
      30            0 : #define GD32_DMA_PERIPH_WIDTH_8BIT        GD32_DMA_CH_CFG_PERIPH_WIDTH(0)
      31            0 : #define GD32_DMA_PERIPH_WIDTH_16BIT       GD32_DMA_CH_CFG_PERIPH_WIDTH(1)
      32            0 : #define GD32_DMA_PERIPH_WIDTH_32BIT       GD32_DMA_CH_CFG_PERIPH_WIDTH(2)
      33              : 
      34              : /* memory data size defined on bits 13-14 */
      35            0 : #define GD32_DMA_CH_CFG_MEMORY_WIDTH(val) ((val & 0x3) << 13)
      36            0 : #define GD32_DMA_MEMORY_WIDTH_8BIT        GD32_DMA_CH_CFG_PERIPH_WIDTH(0)
      37            0 : #define GD32_DMA_MEMORY_WIDTH_16BIT       GD32_DMA_CH_CFG_PERIPH_WIDTH(1)
      38            0 : #define GD32_DMA_MEMORY_WIDTH_32BIT       GD32_DMA_CH_CFG_PERIPH_WIDTH(2)
      39              : 
      40              : /* priority increment offset defined on bit 15 */
      41            0 : #define GD32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15)
      42              : 
      43              : /* priority defined on bits 16-17 as 0, 1, 2, 3 */
      44            0 : #define GD32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16)
      45            0 : #define GD32_DMA_PRIORITY_LOW         GD32_DMA_CH_CFG_PRIORITY(0)
      46            0 : #define GD32_DMA_PRIORITY_MEDIUM      GD32_DMA_CH_CFG_PRIORITY(1)
      47            0 : #define GD32_DMA_PRIORITY_HIGH        GD32_DMA_CH_CFG_PRIORITY(2)
      48            0 : #define GD32_DMA_PRIORITY_VERY_HIGH   GD32_DMA_CH_CFG_PRIORITY(3)
      49              : 
      50              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_GD32_DMA_H_ */