Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2025 Analog Devices, Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_
       8              : 
       9            0 : #define MAX32_DMA_SLOT_MEMTOMEM     0x00U
      10            0 : #define MAX32_DMA_SLOT_SPI0_RX      0x01U
      11            0 : #define MAX32_DMA_SLOT_SPI1_RX      0x02U
      12            0 : #define MAX32_DMA_SLOT_SPI2_RX      0x03U
      13            0 : #define MAX32_DMA_SLOT_UART0_RX     0x04U
      14            0 : #define MAX32_DMA_SLOT_UART1_RX     0x05U
      15            0 : #define MAX32_DMA_SLOT_I2C0_RX      0x07U
      16            0 : #define MAX32_DMA_SLOT_I2C1_RX      0x08U
      17            0 : #define MAX32_DMA_SLOT_ADC          0x09U
      18            0 : #define MAX32_DMA_SLOT_UART2_RX     0x0EU
      19            0 : #define MAX32_DMA_SLOT_SPI3_RX      0x0FU
      20            0 : #define MAX32_DMA_SLOT_SPI_MSS_RX   0x10U
      21            0 : #define MAX32_DMA_SLOT_USB_RX1      0x11U
      22            0 : #define MAX32_DMA_SLOT_USB_RX2      0x12U
      23            0 : #define MAX32_DMA_SLOT_USB_RX3      0x13U
      24            0 : #define MAX32_DMA_SLOT_USB_RX4      0x14U
      25            0 : #define MAX32_DMA_SLOT_USB_RX5      0x15U
      26            0 : #define MAX32_DMA_SLOT_USB_RX6      0x16U
      27            0 : #define MAX32_DMA_SLOT_USB_RX7      0x17U
      28            0 : #define MAX32_DMA_SLOT_USB_RX8      0x18U
      29            0 : #define MAX32_DMA_SLOT_USB_RX9      0x19U
      30            0 : #define MAX32_DMA_SLOT_USB_RX10     0x1AU
      31            0 : #define MAX32_DMA_SLOT_USB_RX11     0x1BU
      32            0 : #define MAX32_DMA_SLOT_SPI0_TX      0x21U
      33            0 : #define MAX32_DMA_SLOT_SPI1_TX      0x22U
      34            0 : #define MAX32_DMA_SLOT_SPI2_TX      0x23U
      35            0 : #define MAX32_DMA_SLOT_UART0_TX     0x24U
      36            0 : #define MAX32_DMA_SLOT_UART1_TX     0x25U
      37            0 : #define MAX32_DMA_SLOT_I2C0_TX      0x27U
      38            0 : #define MAX32_DMA_SLOT_I2C1_TX      0x28U
      39            0 : #define MAX32_DMA_SLOT_UART2_TX     0x2EU
      40            0 : #define MAX32_DMA_SLOT_SPI3_TX      0x2FU
      41            0 : #define MAX32_DMA_SLOT_SPI_MSS_TX   0x30U
      42            0 : #define MAX32_DMA_SLOT_USB_TX1      0x31U
      43            0 : #define MAX32_DMA_SLOT_USB_TX2      0x32U
      44            0 : #define MAX32_DMA_SLOT_USB_TX3      0x33U
      45            0 : #define MAX32_DMA_SLOT_USB_TX4      0x34U
      46            0 : #define MAX32_DMA_SLOT_USB_TX5      0x35U
      47            0 : #define MAX32_DMA_SLOT_USB_TX6      0x36U
      48            0 : #define MAX32_DMA_SLOT_USB_TX7      0x37U
      49            0 : #define MAX32_DMA_SLOT_USB_TX8      0x38U
      50            0 : #define MAX32_DMA_SLOT_USB_TX9      0x39U
      51            0 : #define MAX32_DMA_SLOT_USB_TX10     0x3AU
      52            0 : #define MAX32_DMA_SLOT_USB_TX11     0x3BU
      53              : 
      54              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_ */