Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2024 Analog Devices, Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_
       9              : 
      10            0 : #define MAX32_DMA_SLOT_MEMTOMEM          0x00U
      11            0 : #define MAX32_DMA_SLOT_SPI_RX            0x01U
      12            0 : #define MAX32_DMA_SLOT_UART_RX           0x04U
      13            0 : #define MAX32_DMA_SLOT_I2C_CONTROLLER_RX 0x07U
      14            0 : #define MAX32_DMA_SLOT_I3C_CONTROLLER_RX 0x07U
      15            0 : #define MAX32_DMA_SLOT_I2C_TARGET_RX     0x08U
      16            0 : #define MAX32_DMA_SLOT_I3C_TARGET_RX     0x08U
      17            0 : #define MAX32_DMA_SLOT_AES_RX            0x10U
      18            0 : #define MAX32_DMA_SLOT_SPI_TX            0x21U
      19            0 : #define MAX32_DMA_SLOT_UART_TX           0x24U
      20            0 : #define MAX32_DMA_SLOT_I2C_CONTROLLER_TX 0x27U
      21            0 : #define MAX32_DMA_SLOT_I3C_CONTROLLER_TX 0x27U
      22            0 : #define MAX32_DMA_SLOT_I2C_TARGET_TX     0x28U
      23            0 : #define MAX32_DMA_SLOT_I3C_TARGET_TX     0x28U
      24            0 : #define MAX32_DMA_SLOT_CRC               0x2CU
      25            0 : #define MAX32_DMA_SLOT_AES_TX            0x30U
      26              : 
      27              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_ */